FPGA​/ASIC XXgn Engineer

ASIC/FPGA Engineer

The ASIC/FPGA Engineer will be responsible for developing, implementing, and verifying high-performance communications and networking ASIC/FPGA products.

The role involves architecture design, RTL coding, verification, synthesis, lab validation, and production support. The candidate will work with Ethernet, TCP/IP, and high-speed protocols, translating system requirements into hardware implementations while performing quality checks and debugging at multiple stages of the design flow.

Responsibilities:

• Derive engineering specifications from system requirements and develop detailed architecture.
• Execute design using RTL and/or High-Level Synthesis (HLS, C++ to RTL) and ensure RTL quality via RDC, CDC, Formal, and Lint checks.
• Generate test plans and perform module-level verification, synthesis/STA, lab debug, and SW-driven validation on Linux-based SoC evaluation boards.
• Conduct silicon/FPGA bring-up, characterization, and support production ramp-up, including creation of collateral.
• Candidate tor and provide guidance on EDA tools (CDC, Lint, AC, RDC) and verification methodologies.
• Work hands-on with multiple complex designs from architecture to verification and synthesis.

Requirement/Must Have:

• Bachelor’s Degree in Electrical Engineering or equivalent (Masters + 2 years relevant experience acceptable).
• Minimum 4 years of relevant experience developing, implementing, and verifying high-performance communications/networking ASIC/FPGA products.
• Active SECRET Clearance.
• Proficiency in VHDL design process and FPGA flow (Xilinx FPGA, Vivado).
• Strong knowledge of Ethernet and TCP/IP protocols.
• Hands-on experience in logic/board debugging and analysis.
• Excellent written, verbal, and presentation skills.

XXred Skills / Nice to Have:

• Experience with High-Level Synthesis (Vivado HLS or Candidate tor Calypto).
• Embedded software experience in C++ (OOP) and System Verilog Assertions (SVA).
• Familiarity with high-speed protocols such as PCIe, Ethernet, and TCP/IP.
• Xilinx MPSoC design experience, including SDK/BSP development on bare metal or Peta Linux OS.
• Universal Verification Methodology (UVM) experience.
• Prior experience in Aerospace/Defense.
• Project leadership experience and knowledge of EVM.