SoC Timing; Static Timing Analysis​/STA Engineer, HBM

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Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip‑level timing sign‑off for next‑generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape‑out.

This is a hands‑on senior technical role focused on chip‑level STA ownership, constraint authoring, timing closure, methodology development, and pre‑/post‑silicon timing correlation.

• Own end‑to‑end chip‑level static timing analysis and sign‑off across all checks, modes, corners, and voltage and temperature conditions.
• Develop, maintain, and validate sign‑off quality Synopsys Design Constraints (SDC) for clocks, resets, high‑bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.
• Drive timing closure at block, subsystem, and full‑chip levels through critical path analysis, engineering change orders (ECOs), and close collaboration with physical design on placement, clock tree synthesis, and routing.
• Perform multi‑mode, multi‑corner (MMMC) analysis including clock domain crossing timing, on‑chip variation (OCV, AOCV, POCV), and advanced‑node timing methodologies.
• Lead signal integrity and crosstalk analysis, identify noise‑induced timing issues, and partner with physical design teams on mitigation strategies.
• Build and maintain static timing analysis automation and flows using Python and Tcl for reporting, regression tracking, quality of results dashboards, and sign‑off readiness.
• Conduct post‑silicon timing correlation while defining and driving organization‑wide static timing analysis methodology, sign‑off standards, timing closure best practices, readiness reviews, and tape‑out sign‑off gates, clearly communicating timing status, risks, and closure plans to design leads and senior management.
• Mentor and grow junior engineers, contribute to design documentation and timing sign‑off artifacts, and collaborate cross‑functionally with Physical Design, RTL Design, Verification, Design for Test, Product Engineering, and Test teams to ensure timing requirements are met throughout the design cycle.

• 10+ years of hands‑on experience owning chip‑level static timing analysis and full timing sign‑off on multiple tape‑outs at 5nm or below.
• Deep expertise with industry‑standard static timing analysis tools such as Synopsys Prime Time and/or Cadence Tempus.
• Expert understanding of advanced timing concepts including multi‑mode multi‑corner analysis, on‑chip variation, signal integrity, and power‑aware timing.
• Proven ability to develop and manage complex hierarchical SDC constraints for large systems on chip with multiple clock and power domains.
• Proficiency in Python and/or Tcl scripting for timing flow automation, constraint management, and quality of results reporting.

• Experience with high‑bandwidth memory (HBM), dynamic random‑access memory (DRAM), or memory‑centric system‑on‑chip designs.
• Exposure to design for test timing, including scan, memory built‑in self‑test (MBIST), and Joint Test Action Group (JTAG) interfaces.
• Experience with chiplet‑based or three‑dimensional integrated circuit designs and die‑to‑die interface timing methodologies.
• Familiarity with foundry process design kits, Liberty timing models, and advanced noise and variation modeling.
• Strong communication skills with the ability to present timing status, risks, and sign‑off readiness to cross‑functional teams and senior leadership.

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