HBM Memory Subsystem Architect – MTS​/SMTS​/DMTS

Job Description

You will be responsible for the design & development of next‑generation HBM DRAM products. You will join a multi‑functional group of technical experts working closely with customers, partners, and a distributed team from Build Engineering, Product Engineering, Process Development, Package Engineering, and Business Units. Together, you will complete tasks to ensure the success of our future HBM roadmap.

The HBM Design Architecture group is looking for an experienced Memory Subsystem Architect to work with internal and external partners to investigate, define, and develop innovative new memory subsystem architectures, building on our industry‑leading HBM product solutions.

• Develop innovative memory subsystem frameworks for HBM solutions supporting AI/ML workloads, including PHY, controllers, NOC, microcontrollers, MBIST, interfaces, and adapters.
• Define the requirements for memory and RAS architectures and drive architectural planning for next‑generation memory subsystems.
• Collaborate with internal and external partners to develop novel architectures and detailed IP requirements.
• Lead engagement with IP vendors, including evaluation and selection of interface and functional IP.
• Analyze benchmarks, workloads, and simulations to identify opportunities for performance, efficiency, and architectural innovation.
• Model performance, performance/watt, gate count, power, and area; create architectural and external‑facing specifications aligned with protocol and hardware standards.
• Partner with RTL, validation, and product teams to ensure timely and successful implementation, participating in design reviews for HBM and memory subsystem features.
• Drive microarchitecture definition, participate in performance simulation and benchmarking, and debug issues across models, RTL, and IP.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 15 years of experience in memory subsystem architecture and design.
• Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM).
• Experience with PHY design and understanding of signal integrity issues.
• Familiarity with industry‑standard bus protocols such as AXI, AMBA, AHB, DFI, etc.

• PhD or equivalent experience in a relevant field.
• Familiarity with EDA tools for design and verification.
• Practical experience with multi‑core systems, coherent interconnects & Industry IO protocol like PCIe/CXL, confidential compute, virtualization & security.
• Knowledge of serial link protocols (UCIe etc.) is desired.