SMTS Design Verification Engineer

Responsibilities

• DV Planning: Develop and maintain the full-chip DV plan covering all soft IP blocks and top-level integration; define coverage targets, test priorities, and sign-off criteria in alignment with the Chip Lead.

• Testbench Development: Build and maintain UVM/System Verilog verification environments for all key design blocks including I2C and register interface, PRBS-based Error Counting logic, Eye Monitor control state machine, PHY configuration and control register file (CSR / APB or equivalent), and top-level chip integration and block interconnect.

• Test Development: Write directed tests for corner cases and protocol compliance; develop constrained-random test scenarios with appropriate coverage models; achieve and document functional and code coverage closure.

• Assertion-Based Verification: Implement System Verilog Assertions (SVA) for critical control sequences, protocol compliance, and reset/initialization behavior in coordination with the Chip Lead.

• Formal Verification: Apply formal property checking (Jasper Gold or VC Formal) where applicable — CSR correctness, CDC properties, reset verification.

• Regression Management: Build and maintain regression infrastructure; triage failures, root-cause issues to RTL or testbench, and track bug closure through the design team.

• Post-Silicon Support: Provide debug waveforms, expected behavior documentation, and test vectors to support ATE development and lab bring-up in coordination with the Lab Guru.

• DV Documentation: Maintain verification plan, coverage closure reports, and test methodology documentation to support program continuity and follow-on chip development.

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field

• 6–12 years of functional verification experience in a UVM/System Verilog environment

• Demonstrated experience building UVM testbench environments from scratch — not just maintaining or extending existing infrastructure

• Experience verifying serial management interface blocks — I2C, SPI, APB, AHB, or equivalent

• Strong coverage-driven verification methodology — functional coverage modeling, code coverage analysis, and coverage closure documentation

• Solid debugging skills across simulation waveforms and RTL — ability to distinguish RTL bugs from testbench issues quickly and efficiently

• Comfortable working on a small team with a high degree of individual ownership and accountability

• Experience with formal property verification (Jasper Gold, VC Formal, or equivalent) for block-level sign-off

• Familiarity with PHY functional modeling or behavioral simulation, including use of vendor-supplied behavioral models or BFMs in a mixed-signal simulation context

• Experience with real-number modeling (RNM) or Verilog-AMS behavioral models for analog block abstraction in digital simulation environments

• Familiarity with PRBS pattern generation and error detection verification — understanding the algorithmic behavior being verified, not just the bus protocol

• Post-silicon validation experience — candidates who have carried verification knowledge into the lab and supported bring-up and debug on real silicon are strongly preferred

• Experience developing ATE test vectors or correlating simulation results to production test programs

• Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart

$ - $ a year

Additional compensation may include benefits, bonuses and equity.

Micron offers a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.