Principal SoC DFT Engineer, HBM

As a Principal SoC DFT Engineer within the Heterogeneous Integration Group (HIG), you will be responsible for the DFT architecture, implementation, and signoff of complex HBM base-die System-on-Chip (SoC) designs. This role is part of the SoC execution team, working closely with RTL design, verification, physical design, and product engineering to ensure robust, scalable, and manufacturable test solutions from pre‑silicon development through tapeout and product bring‑up.

• Own SoC-level DFT implementation, including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base‑die designs.
• Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at the block, subsystem, and full‑chip levels, working closely with RTL and integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
• Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring‑up.
• Support pre‑silicon debug of DFT‑related issues and assist with post‑silicon bring‑up and yield/debug analysis.
• Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.

• Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field.
• 7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
• Job title and level can scale depending on experience and qualifications.

• Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
• Familiarity with full RTL‑to‑GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
• Experience working with large, complex SoCs involving multiple IPs and subsystems.
• Proficiency with industry‑standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation.

The US base salary range that Micron Technology estimates it could pay for this full‑time position is:

$ - $ a year

Additional compensation may include benefits, bonuses and equity.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. Micron offers a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.

Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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