HBM SoC Physical Design Engineer

Key Responsibilities

• Own physical implementation for SoC blocks and/or top‑level, including floor‑planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi‑mode/multi‑corner scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Integrate and implement complex IP such as controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, and PHY‑adjacent logic with a focus on robust physical integration and timing/power integrity.
• Perform and coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
• Partner with DFT teams to ensure scan/MBIST requirements are physically realizable without compromising PPA or schedule.
• Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
• Support tape‑out execution (checklists, ECO flows, signoff reviews) and contribute to post‑silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best‑practice methodology development.

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
• Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/Prime Time, Siemens Calibre or equivalent.
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew).
• Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
• Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop engineers early in their careers.

• Experience with HBM / DRAM adjacent SoC designs or memory‑subsystem‑heavy SoCs.

• Choice of medical, dental, and vision plans available in all locations.
• Benefit programs that protect income if unable to work due to illness or injury.
• Paid family leave.
• Robust paid time‑off program and paid holidays.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.