Principal Engineer

Responsibilities

• Lead floor-planning process with emphasis on placement, routing optimization, PDN planning, distribution, and TSV placement.
• Execute APR layout to ensure efficient component placement and routing.
• Optimize design rules for cost, performance, and functionality.
• Collaborate with Architecture, Process Integration, CAD, Probe, and Assembly teams to define and implement design methodologies and flows.
• Conduct timing analysis and power analysis to meet performance and reliability requirements.
• Analyze power networks to identify and mitigate IR drop and electromigration issues.
• Perform layout verification tasks including LVS, DRC, and Antenna checks.
• Conduct quality checks and maintain documentation.
• Demonstrate leadership in planning, area/time estimation, scheduling, delegation, and execution to meet project milestones.
• Verify power networks using TOTEM at post-layout for compliance with design specifications and reliability standards.
• Lead reticle experiments and manage tape-out revisions.
• Participate in design reviews and provide feedback to improve design quality.
• Debug and resolve physical design issues in collaboration with engineering teams.
• Provide experienced technical knowledge to advance innovative solutions.
• Advise senior management on significant technical issues.

• Bachelor’s degree in Electrical Engineering, Electronic Engineering, or related field, followed by 8 years of progressive, post-baccalaureate experience in the job offered or an Engineering-related occupation.
• CMOS process experience in analog layout fundamentals, including Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices.
• Layout skills using Cadence Virtuoso and Cadence Virtuoso XL.
• Layout methodology from initial chip plan to tape‑out.
• Calibre layout verification tools.
• ASIC style design flows, including floor‑planning, synthesis, place/route, layout verification, static timing analysis, and formal/layout verification - flows/processes.
• Cadence layout tools, including Innovus or Tempus or Synopsys, including ICC2 or Prime Time.
• PDN design and evaluation using tools such as TOTEM, Red Hawk, or BSEE.

• Choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Benefit programs that protect income if unable to work due to illness or injury, and paid family leave.
• Robust paid time‑off program and paid holidays.
• Additional information regarding available benefit programs can be found in the Benefits Guide posted on

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.