SMTS Analog Design Engineer, Mixed-Signal PHY; Clocking Speed I​/O

Position: SMTS Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)
Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Micron's Interface Pathfinding team operates at the leading edge of that mission - driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3-5 year technology horizon. As a Principal Analog Design Engineer, you will be a core technical contributor on a small, senior team spanning analog design, layout, silicon characterization, digital design, and physical design - united around the goal of preparing high-speed interface innovations for high-confidence product adoption.

The analog design scope is broad and deep, with clocking as a primary technical focus, but the program values engineers who bring perspective across the full signal chain. Key design domains include clocking architecture (PLL/DLL, clock distribution, jitter budgeting, clock recovery), transmitter design (high-speed output drivers, pre-emphasis, swing/impedance control), receiver design (sense amplifiers, CTLE/DFE equalization, samplers), bias and reference generation, and calibration architecture.

The circuits are custom and original - this is not integration or maintenance work. The goal is to push the boundaries of what is possible in high-speed signaling and validate those boundaries with real hardware data.

This is a long-term opportunity on an active program with real momentum - strong execution early is expected to lead to follow-on projects of increasing scope and complexity.

Responsibilities

* Circuit Design:
Own the design of one or more custom analog blocks from specification through schematic, simulation, and layout review - with clocking (PLL, DLL, CDR) as the primary focus and transmitter/receiver circuits as valued secondary experience.

* Architecture Definition:
Contribute to top-level PHY analog architecture decisions - clocking topology, signal chain partitioning, power domain strategy, and performance/area/power tradeoffs.

* Simulation & Verification:
Develop and maintain transistor-level simulation test benches; execute corner, Monte Carlo, and mismatch analysis to characterize design margin and yield sensitivity.

* Analog-Digital Interface:
Define clean interface specifications between custom analog blocks and the digital control wrapper - signal naming, timing contracts, and boundary constraint documentation in coordination with the Chip Lead.

* Layout

Collaboration:

Work closely with the layout team to review and guide custom analog layout - matching, shielding, guard ring, and parasitic sensitivity for high-speed circuits.

* Silicon Bring-Up:
Support post-silicon characterization in the lab - correlating measured results to simulation, identifying root causes of performance delta, and extracting maximum learning from each hardware run.

* Design Documentation:
Author block-level specifications, simulation summary reports, and interface control documents that serve as the authoritative reference for the team and for follow-on program development.

Basic Qualifications

* BS, MS, or PhD in Electrical Engineering or related field (MS/PhD strongly preferred for this level)

* 10+ years of analog/mixed-signal IC design experience with at least one tape-out in a primary circuit ownership role

* Deep expertise in clocking circuit design - PLL, DLL, or CDR architecture and transistor-level implementation in advanced CMOS nodes

* Strong transistor-level simulation skills using HSpice or equivalent; comfort with corner, Monte Carlo, and mismatch analysis for yield-aware design

* Solid understanding of jitter analysis - phase noise, period jitter, cycle-to-cycle jitter, and their impact on high-speed link timing margins

* Experience defining analog-digital interfaces in a mixed-signal environment - including timing contracts, reset/initialization sequencing, and digital control of analog parameters

* Ability to work effectively as a peer technical contributor on a small team - comfortable with broad ownership, cross-discipline collaboration, and making design decisions with real consequences

* Strong written communication skills - this role produces specifications and simulation reports, not just schematics

Preferred Qualifications

* Experience with high-speed transmitter design - output driver architectures, pre-emphasis, swing control, and impedance matching for multi-Gbps die-to-die or Ser Des interfaces

* Experience with high-speed receiver design - sense amplifiers, CTLE/DFE equalization, sampler design, and threshold calibration

* Familiarity with die-to-die or chip-to-chip PHY architectures - UCIe, AIB, BoW, or proprietary short-reach interconnect standards

* Experience with OTP/fuse-based calibration architectures and analog trim loop implementation

* Familiarity with real-number modeling (RNM) or Verilog-AMS…