Sr. Member Technical Staff - ESD and Latch-Up - HBM

Responsibilities

• Define end‑to‑end ESD and latch‑up architecture across base die, DRAM die, and interconnects
• Develop protection strategies for high‑speed I/O, TSV interfaces, and advanced packaging
• Establish ESD/LUP standards, rule decks, and sign‑off criteria
• Drive correlation between design assumptions, silicon validation, and field reliability
• Partner with foundry and packaging teams on system‑level ESD challenges

• MS or PhD in Electrical Engineering or related field, or equivalent practical experience
• 10+ years of experience in ESD and latch‑up design and reliability
• Expertise in advanced CMOS technologies such as FinFET or GAA
• Experience with 3D IC, TSV, or die‑to‑die interfaces

• Experience defining architecture across multi‑die or stacked memory systems
• Background in ESD device or circuit design
• Experience developing PDK collateral or ESD rule decks
• Experience debugging silicon failures related to ESD or latch‑up
• Demonstrated technical leadership across cross‑functional teams

Base salary range: $ – $ per year. Additional compensation may include benefits, bonuses, and equity.

Micron offers medical, dental, and vision plans, income protection, paid family leave, a robust paid time‑off program, and paid holidays.

Micron is a proud equal opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws.

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