Design Infrastructure Engineer; Standard and Custom Cell Characterization-HBM

Design Infrastructure Engineer (Standard and Custom Cell Characterization) – HBM

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. These designs use Through Silicon Via (TSV) technology, stacking multiple DRAM chips on a high‑speed memory controller with coordinated logic in a single package.

The aim is to deliver the lowest power per bit solutions in the industry.

Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic designs. This role involves characterizing standard and custom cells across multiple process technologies, including Micron’s internal nodes and external foundries such as TSMC. The role supports several HBM product lines, including HBM DRAM dies, logic dies (JEDEC and custom variants), and advanced 3D HBM architectures.

You will operate at the intersection of circuit design, EDA infrastructure, and silicon validation readiness, delivering robust, scalable, and high‑quality characterization flows that directly impact timing closure, power modeling, and product quality across next‑generation HBM programs.

• Develop and maintain scalable infrastructure for standard cell and custom cell characterization, including timing, power, noise, and signal integrity modeling.
• Build reusable, automated flows to support multi‑corner, multi‑mode (MCMM) characterization across extensive PVT spaces, and enable robust Liberty model generation, validation, and regression frameworks to ensure high‑quality results for downstream design and signoff flows.
• Enable characterization across heterogeneous process technologies, addressing technology‑specific challenges such as variability, layout‑dependent effects, aging, and reliability, and driving consistent methodologies that allow seamless portability and standardization across multiple process nodes.
• Support characterization requirements across diverse HBM product verticals, collaborating with design teams to define requirements for specialized circuit classes such as TSV interfaces, PHY‑critical paths, and high‑speed datapath elements, ensuring alignment with system‑level performance and power targets.
• Integrate characterization flows into broader design and verification ecosystems by partnering with design, verification, and CAD teams. Drive improvements in model accuracy, turnaround time, and silicon correlation while establishing standard processes for corner definition, quality metrics, and data consistency across IPs and programs.
• Lead debug, validation, and continuous improvement efforts by root‑causing mismatches between SPICE, extracted views, STA, and silicon behavior. Develop metrics, dashboards, and automated checks to ensure completeness, adaptability, and quality of characterization data, enabling reliable signoff and scalable deployment across future HBM programs.

• Bachelor’s or Master’s Degree in Electrical Engineering or a related field, with strong fundamentals in CMOS digital and mixed‑signal circuit design, device physics, and PVT variation.
• Hands‑on experience with standard or custom cell characterization flows—including Liberty modeling (CCS/ECSM or equivalent) and SPICE‑based simulation.
• Solid understanding of STA flows and timing libraries, combined with proficiency in scripting languages such as Python, Perl, or Tcl for automation.
• Experience in Silicon Smart or Prime Lib.

• Experience working across multiple semiconductor process technologies.
• Experience in HBM, DRAM, or high‑speed interface design, particularly with advanced foundry PDKs such as TSMC nodes.
• Familiarity with high‑speed PHY design, TSV‑aware design considerations, and advanced modeling topics such as signal integrity, EMIR effects, aging, and reliability.
• Prior exposure to infrastructure or methodology development beyond using characterization flows.
• Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.