SoC Physical Verification Engineer, HBM

Physical Verification Engineer

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Physical Verification Engineer, you will be a key technical contributor within the Heterogeneous Integration Group (HIG), responsible for defining, executing, and driving sign-off quality physical verification flows for next-generation HBM logic die and memory-centric SoCs. You will work across physical design, design rule development, EDA tool teams, foundry interfaces, and product engineering teams to deliver industry-leading, tape-out-ready silicon under aggressive schedule, quality, and reliability constraints.

This role combines full-chip physical verification ownership — including DRC, LVS, ERC, and DFM — with deep collaboration across implementation and silicon bring-up, ensuring design integrity from layout through first silicon.

Responsibilities will include, but are not limited to:

• Lead end-to-end physical verification sign-off for full-chip and hierarchical designs, including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), Physical Electrical Rule Check (PERC), antenna checking, and Design for Manufacturability (DFM).
• Execute and debug foundry-qualified rule decks, manage waivers, and drive clean closure while ensuring compliance with advanced-node foundry requirements.
• Perform reliability verification across multiple power domains, including electrostatic discharge (ESD), latch-up, electromigration, floating nets, and connectivity checks.
• Run density, metal fill, and chemical mechanical polishing (CMP) checks to ensure yield-aware manufacturability at 3 nanometer and below.
• Perform parasitic resistance-capacitance (RC) extraction and support correlation of physical verification results with post-silicon measurements.
• Develop, maintain, and optimize physical verification flows, automation, and regression infrastructure using Python, Tcl, Perl, or similar scripting languages.
• Drive adoption of machine learning (ML) and artificial intelligence (AI)-based physical verification and power-performance-area (PPA) optimization tools.
• Partner with physical design, custom layout, computer-aided design (CAD), register-transfer level (RTL), product engineering, EDA, and foundry teams, including direct interface with TSMC, from design kick-off through tape-out readiness and sign-off decision gates.
• Leveraging AI to develop AI assisted development workflows.

Minimum Qualifications:

• Strong experience with full-chip or block-level physical verification for advanced-node system-on-chip, memory, or heterogeneous integration designs.
• Deep hands-on expertise in physical verification methodologies, including DRC, LVS, ERC, PERC, DFM, antenna, and reliability sign-off.
• Experience using industry physical verification tools such as Calibre, IC Validator (ICV), Pegasus, or similar, including rule deck development or customization.
• Working knowledge of full RTL-to-GDS implementation flows, including place-and-route, extraction, and their impact on physical verification outcomes.
• Ability to drive verification closure through strong cross-functional communication in a global engineering environment.
• Proficiency with leveraging AI and AI-enabled development workflows.

Preferred Qualifications:

• Experience with high-bandwidth memory (HBM), DRAM, or memory-centric system-on-chip physical verification, including multi-die, chiplet, or 2.5D/3D integration.
• Background in GPU, CPU, or high-performance accelerator physical implementation at advanced process nodes with aggressive sign-off and tape-out schedules.
• Familiarity with foundry design rule documents, front-end-of-line (FEOL) and back-end-of-line (BEOL) rules, and advanced design for manufacturability best practices.
• Exposure to post-silicon failure analysis, yield learning, or layout-based debug with correlation between physical verification results and silicon behavior.
• Master's or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience,…