Senior Lead, DFT and Test Engineer

General Overview

Celestica is seeking a Sr. Lead, DFT and Test Engineer to ensure testability and maximum test coverage are embedded into hardware design long before layout freeze. In this role within our DFx Center of Excellence, you will perform in-design testability reviews, audit test point access and boundary scan chains, and model structural and functional test coverage against key manufacturing targets to drive high-yield, debug-ready releases.

Celestica is seeking a Sr. Lead, DFT and Test Engineer to ensure testability and maximum test coverage are embedded into hardware design long before layout freeze. In this role within our DFx Center of Excellence, you will perform in-design testability reviews, audit test point access and boundary scan chains, and model structural and functional test coverage against key manufacturing targets to drive high-yield, debug-ready releases.

• Pre-Freeze Audits: Review schematics and PCB layouts against the core DFT rule set prior to layout freeze, documenting findings backed by technical evidence.

• Coverage Modeling: Model structural and functional coverage against the Manufacturing Test Requirements Specification (MTRS) and quantify coverage gaps.

• Finding Disposition: Partner directly with hardware design and software teams to resolve testability issues through test point additions, boundary scan chain corrections, or agreed-upon design alternatives.

• Validation & Verification: Verify actual achieved coverage on the first physical test fixture and document discrepancies against pre-layout claims.

• Site Support: Assist with functional test definition and early build debug in collaboration with Technical Region Leads (TRLs) and local test SMEs.

• Rule Evolution: Propose targeted DFT rule set updates derived from test escapes and post-build fixture rework.

• Formal testability reviews and fully dispositioned DFT findings.

• Structural and functional coverage models mapped against the MTRS.

• Empirical evidence packages for achieved coverage on first fixtures.

• Formal DFT rule set change proposals.

This position focuses strictly on testability as a core design property. It is not a test software development role, nor is it a physical fixture design position.

• Total designed-in coverage achieved on the first physical fixture.

• Complete resolution and closure of DFT findings prior to layout freeze.

• Minimization of test escapes and repeat testability issues across product lines.

• Background in Design for Testability (DFT), board-level schematics, and high-density PCB layout checks.

• Experience evaluating boundary scan chains, debug/provisioning access, and test point accessibility.

• Practical knowledge of MTRS coverage modeling, functional test strategy, and hardware bring-up.

• Duties of this position are performed in a normal office environment.

• Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.

• Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.

• Occasional travel may be required.

• 4 to 6 years in a similar role or industry.

Bachelor degree or consideration of an equivalent combination of education and experience.

Educational Requirements may vary by Geography

This job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time.

Celestica is an Equal Opportunity Employer. All…