Signal Integrity Engineer (Entry to Senior level

Your Job

As an SI Interconnect Engineer, you will work at the intersection of mechanical design and electrical performance. You will support the development of next-generation interconnect solutions (such as USB-C, HFM,HSAL-G, HS-Max, PCIexpress and other physical layer solutions) by using advanced 3D electromagnetic (EM) simulation tools and high-frequency lab equipment, VNA, TDR and others. Your goal is to ensure that Molex products maintain signal integrity across demanding automotive and data center environments within the product and throughout the whole channel.

Molex CMS Networking team is a leader in Interconnect solutions in providing data connectivity solutions in transportation industry in the area of high speed. In this role, you aren't just placing components; you are designing the components that make modern technology possible. You will gain exposure to and lead in the following areas:

• Automotive high-speed links (Self-driving car data backbones).
• Automotive Ethernet, Ser, Deser and other systems
• Complex Material Science, material selection (How different plastics and plating affect signals).

• 3D EM Simulation & Modeling
  • Full-Wave Modeling:
    Assist in creating high-fidelity 3D models of connectors and cable terminations using Ansys HFSS or CST Studio Suite.
  • Virtual Prototyping:
    Run simulations to extract S-parameters and identify impedance discontinuities within the connector pin-field and mating interface.
  • Optimization:
    Perform "what-if" analyses on mechanical variables (e.g., pin geometry, plastic dielectric constants, shield spacing) to optimize return loss and crosstalk.
• Lab Validation & Characterization
  • High-Frequency Measurement:
    Use Vector Network Analyzers (VNA) and Time Domain Reflectometers (TDR) to characterize physical prototypes up to 20 GHz or higher.
  • Fixture De-Embedding:
    Learn and apply de-embedding techniques (like AFR or TRL) to remove the effects of test boards, isolating the performance of the connector itself.
  • Correlation:
    Compare lab measurement data against simulation models to validate accuracy and refine simulation methodologies.
• Crosstalk Simulation & Discovery (Pre-Silicon/Pre-Layout)
  • Aggressor-Victim Analysis:
    Use Ansys HFSS to perform "discovery" simulations identifying the most significant crosstalk contributors within a high-density pin array.
  • NEXT/FEXT Modeling:
    Extract Near-End Crosstalk (NEXT) and Far-End Crosstalk (FEXT) S-parameters to determine the isolation levels between differential pairs.
  • ICN Calculation:
    Calculate Integrated Crosstalk Noise (ICN) and Power Sum Crosstalk to evaluate total noise interference against IEEE 802.3 or OIF-CEI limit lines.
  • Pin-Map Optimization:
    Based on crosstalk discovery, provide recommendations for optimized signal-to-ground ratios and pin-mapping (e.g., G-S-S-G patterns) to shield sensitive high-speed lines.
• Crosstalk Validation (Lab/Post-Layout)
  • Multi-Port Measurements:
    Utilize 4-port or 8-port Vector Network Analyzers (VNAs) to measure real-world crosstalk in physical prototypes and connector mating interfaces.
  • Time Domain Analysis:
    Use TDR/TDT to locate the exact physical location of a crosstalk "hotspot" within a connector body or cable transition.
  • Correlation:
    Document discrepancies between simulated crosstalk and measured crosstalk, investigating factors such as manufacturing tolerances in pin-to-pin spacing or plating consistency.
• Data Analysis & Automation
  • Scripting:
    Utilize Python or MATLAB to automate the processing of large Touchstone sNp file datasets.
  • Compliance Testing:
    Analyze simulation and test results against industry standards such as IEEE 802.3 (Ethernet), USB4, or USCAR-2 specifications.
• Documentation & Collaboration
  • Technical Reports:
    Prepare professional SI reports summarizing performance vs. specifications for internal design reviews.
  • Cross-Functional Support:
    Interface with Mechanical Engineers to explain how physical design changes impact electrical performance.

• Currently pursuing a M.S. or Ph.D. in Electrical Engineering or Physics with coursework focused in Electromagnetics, Microwave Engineering, or Circuit Theory.
• 2 to 5 years of experience (With M.S. in Electrical Engineering / Physics) OR 1 to 3 years of experience (With PhD in Electrical Engineering / Physics)
• Strong desire to understand the "why" behind signal degradation.
• Ability to translate complex EM concepts into actionable design advice for mechanical teams.

• Understanding of transmission line theory, characteristic impedance and S-parameters.
• Exposure to CST, Ansys HFSS, ADS, or Cadence Sigrity.
• Basic proficiency in programming such as Python (Num Py, Pandas, Matplotlib) or MATLAB.
• Basic experience with oscilloscopes or VNAs is a significant plus.

At Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by…