Senior Digital Verification Engineer - UVM​/System Verilog

Overview

We are partnered with a global leader in high-speed optical networking and telecommunications connectivity solutions. The team is looking to hire a Senior Digital Verification Engineer to simulate and validate high-performance subsystems for their flagship optical products.

This is a permanent working opportunity based in Rochester, New York.

• Collaborate with systems engineers to define and implement verification strategies for complex functional blocks.
• Build robust testbench environments, components, agents, and scoreboards using System Verilog UVM or
  
  C.
• Author comprehensive verification, functional coverage, and formal verification test plans.
• Run coverage-driven verification, monitor regressions, and debug failures alongside the digital design team.
• Take complete accountability for the functional validation of major architectural blocks using simulation and formal methods.

• Advanced expertise with System Verilog, System Verilog Assertions (SVA), and major EDA simulation tools.
• Experience with UVM and formal verification methods (highly preferred).
• Background in Digital Signal Processing (DSP), Forward Error Correction (FEC), or protocols like OTN and Ethernet.
• Proficiency in scripting and programming languages (Python, C/C++, Make, Git).
• Degree in Electrical Engineering, Computer Science, or a related scientific discipline.
• Highly motivated self-starter with a methodical approach to complex problem-solving.

Senior Digital Verification Engineer / System Verilog / UVM / SVA / ASIC / SoC / DSP / FEC / Optical Networking / OTN / Ethernet / Simulation / Rochester / New York / Semiconductor