ASIC Design Verification Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.

The focus of this role is to own the verification strategy and coverage closure for AMD's mixed-signal power management IP, driving system-level verification of the full SOC while also contributing block-level verification and RTL design.

You have a passion for finding bugs. You think in terms of coverage, corner cases, and what has not been exercised yet. You are comfortable reading RTL as well as writing test benches, and you enjoy working at the boundary between digital and analog. You are a team player with excellent communication skills, strong analytical and problem-solving ability, and the persistence to chase an intermittent failure to root cause.

• Own the overall verification strategy, test plan, and coverage closure for a mixed-signal power management IC

• Define functional and code coverage goals, track progress against them, and report verification status and readiness to the project team

• Own verification signoff criteria and drive the team to coverage closure ahead of tape-out

• Maintain and improve regression infrastructure, triage flow, and results reporting

• Develop and execute system-level verification of the full SOC, including boot and reset sequencing, power state transitions, fault and protection scenarios, and host interface traffic

• Verify firmware-driven behavior in co-simulation of embedded firmware with RTL

• Build and maintain System Verilog/UVM testbench components, sequences, checkers, and assertions at the system level

• Develop block-level test benches and coverage for digital blocks as project needs require

• Verify digital/analog interfaces using real-number models (RNM) of analog macros, including model bring-up, correlation to analog behavior, and debug in the digital simulation environment

• Partner with Analog Design and RTL Design to review model fidelity and ensure the verified behavior matches silicon intent

• Partner with RTL designers on design reviews, verification planning, and debug of failures to root cause

• Contribute to System Verilog RTL design work across the team as needed

• Support post-silicon bring-up, including correlation of silicon behavior back to pre-silicon test cases

• Work across Analog, Firmware, Systems Engineering, and Architecture teams; mentor junior engineers on verification methodology

• System-level or SOC-level verification ownership on a mixed-signal device

• Real-number modeling (RNM) of analog blocks in System Verilog (wreal /nettype real), or experience with Verilog-AMS

• System Verilog RTL design experience in an ASIC environment

• Firmware/RTL co-simulation or hardware/software co-verification experience

• Formal verification, assertion-based verification (SVA), or emulation/FPGA prototyping experience

• Post-silicon bring-up and debug experience

• Experience mentoring engineers and leading verification reviews

• Strong System Verilog and UVM testbench development skills, with ownership of verification for a block or subsystem through tape-out
• Demonstrated experience defining verification plans and driving functional and code coverage to closure
• Proficiency with simulation, coverage, and debug tools, and with regression automation
• Ability to read and understand RTL and design specifications to independently derive test intent

• Bachelors or master's in electrical/computer…