Senior Hardware​/Software Design Engineer; HSDE

Job Summary

Our LOE program provides our customer’s Signals Analysis organization with the best possible solutions for their mission needs. We achieve this through rapid prototyping, new development, and advanced technology research. From leading‑edge visualizations to analytic development, we’re always pushing the boundaries to find new and better data sources and tradecraft to answer intelligence questions. With a focus on collaboration and a fast‑paced environment, our prototype development program is the ideal place to grow your skills and make a real impact.

Senior Hardware/Software Design Engineer in the Intelligence Sector’s Cyber & Analytics Business Area (CABA). Design, develop, construct, and test electronic hardware (FPGA) and software processing components for subsystems supporting RF communication and collection systems. Requires expertise in FPGA development, digital signal processing implementation, and software‑hardware integration to support mission‑critical requirements. Lead technical design efforts, implement DSP algorithms and associated technical components in FPGA hardware, integrate with existing Linux codebases, bridge FPGA to software stack, and document all efforts.

• Up to a $25,000 cash sign‑on bonus or a paid time‑off bonus.

• Implement DSP and associated technical components in FPGA for code-base integration.
• Lead hardware design, including FPGA RTL development, timing closure, and resource optimization.
• Integrate FPGA with Linux codebases and bridge FPGA to software stack.
• Develop and manage system‑level software integration.
• Document all design and implementation efforts.

• Bachelor’s degree plus 8 years of relevant experience or equivalent.
• Strong experience in FPGA coding, digital signal processing theory & application, and interfacing FPGA code with existing codebases and software.
• Knowledge of signal‑processing blocks and related DSP components.
• Proficiency with Linux OS and coding ability in C and C++.
• Experience with Vivado required; experience with Epiq Solution PDK preferred.
• Active TS/SCI security clearance with polygraph required.

$ – $ (general guideline only; final compensation depends on responsibilities, experience, and internal equity).

Competitive compensation, health and wellness programs, income protection, paid leave and retirement plans. Additional benefits include paid time off, 11 paid holidays, 401(k) with 6% company match and immediate vesting, flexible schedules, discounted stock purchase plans, technical up‑skilling, education and training support, and parental paid leave.

All qualified applicants will receive consideration for employment without regard to sex, race, ethnicity, age, national origin, citizenship, religion, physical or mental disability, medical condition, genetic information, pregnancy, family structure, marital status, ancestry, domestic partner status, sexual orientation, gender identity or expression, veteran or military status, or any other basis prohibited by law. Leidos will also consider for employment qualified applicants with criminal histories consistent with relevant laws.