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Senior ASIC RTL Design Engineer Speed Networking

Job in Roseville, Placer County, California, 95678, USA
Listing for: Hewlett Packard Enterprise Development LP
Full Time position
Listed on 2026-03-04
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: Senior ASIC RTL Design Engineer – High-Speed Networking
A leading technology firm in California seeks a Senior RTL Design Engineer for their HPE Networking ASIC organization. The role involves ASIC development, working closely with Physical and Verification teams. Candidates must have a Bachelor's degree in Electrical Engineering and 10+ years of industry experience, alongside strong coding skills in Verilog/System Verilog. This position offers opportunities for professional growth in a fast-paced environment.
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Position Requirements
10+ Years work experience
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