ASIC Senior Design Engineer

We are looking for a
** Senior RTL Design Engineer
** to join our HPE Networking ASIC organization.  As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex blocks where you can challenge yourself and grow.
** Responsibilities:
** Work with Physical design team for optimal floorplan and timing closure. Identify and fix timing in RTL to meet the frequency target.
· Work with the Verification team to make sure your block is fully validated.
** Recommended skills
** Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 10+ years of relevant experience.
· Strong analytical/ problem solving skills.
· Demonstrated skills in leading and implementing high performance modules from specification to final netlist. Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.
· Strong coding skills in Verilog/System Verilog through previous work experience are necessary.  Knowledge of synthesis/lint and other state-of-the-art EDA tools used in typical ASIC development process is highly desired.
· Excellent written and verbal communications skills is necessary.
· Knowledge of Perl/Python is strongly desired.  HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together.

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** Hewlett Packard Enterprise
** Technology innovation that fosters business transformation.

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