Sr. ASIC Design Engineer
Listed on 2026-05-10
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Engineering
Systems Engineer, Software Engineer
Job Location
This role has been designed as "Onsite" with an expectation that you will primarily work from an HPE office.
Company OverviewHewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next.
We value diverse backgrounds and empower our employees to manage work and personal needs, fostering a collaborative and innovative environment.
HPE Networking is a leading provider of advanced routers and switches for the internet. In the Silicon Group, you will work on cutting‑edge networking chips that power high density routers and switches. The role involves building high‑speed ASICs, from specifications to final netlist, working with complex modules and subsystems.
Responsibilities- Start with a functional specification of a module and produce a detailed micro‑architecture specification that meets power and area requirements.
- Implement the design using Verilog or System Verilog.
- Write functional coverage/SVA to help verification capture corner‑case bugs.
- Collaborate with the Physical Design team for optimal floorplan and timing closure; identify and fix timing in RTL to meet the frequency target.
- Work with the Verification team to ensure your block is fully validated.
- Mentor and provide guidance to new college‑grad engineers and interns, improving leadership skills.
- Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 5+ years of relevant experience.
- Strong analytical and problem‑solving skills.
- Knowledge of computer architecture and networking protocols through graduate coursework or prior work is a plus.
- Strong coding skills in Verilog/System Verilog through projects and previous work experience.
- Knowledge of synthesis/lint and other state‑of‑the‑art EDA tools is desired.
- Excellent written and verbal communication skills.
- Knowledge of Perl/Python is a plus.
- Experience with AI agentic tools is a plus.
Health & Wellbeing
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We strive to provide a comprehensive suite of benefits that supports physical, financial, and emotional wellbeing for you and your loved ones.
Personal & Professional Development
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We invest in your career with programs that help you reach any career goals, whether becoming a knowledge expert or applying your skills to another division.
Unconditional Inclusion
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We celebrate individual uniqueness and provide flexibility to manage work and personal needs while fostering a bold, collaborative environment.
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based on geographic location, work experience, education/training, and/or skill level.
United States of America:
Annual Salary USD 153, in California. The listed salary range reflects base salary. Variable incentives may also be offered.
HPE is an Equal Employment Opportunity/Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are based on qualifications, merit, and business need. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring consideration of qualified applicants with criminal histories.
NoFees Notice & Recruitment Fraud Disclaimer
Hewlett Packard Enterprise and its authorized recruitment agencies will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Candidates are solely responsible for verifying any hiring agency that claims to work with HPE. HPE disclaims liability for any damages or claims that may result from fraudulent representations.
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