Senior Technical Staff Engineer - Design; IO

Job Description

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit  has a broad portfolio of products widely deployed by industry’s cutting‑edge server/storage OEMs and hyperscale data centers. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world’s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers.

Join a team where you can expand your skill set and drive key elements of the industry’s technology leadership.

As a Staff/Sr. Staff Design Engineer, your job will entail the following:

• Design planning of pad rings and package substrates, bump pattern construction.
• Dynamically define and optimize pad ring connectivity.
• Work with CFTs (Cross‑Functional Team) on the deliverables (DEF, Verilog netlist, etc.).
• Interface with and support Architect, PD, PE, technology development and foundries teams.
• Support JTAG TAP controller integration and implementation across SoC designs, ensuring IEEE 1149.1 compliance and proper JTAG signal connectivity in collaboration with the DFT team.
• Collaborate with CFTs on TAP controller operation, scan‑enable path handling, and post‑silicon debug requirements.
• Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds.

• B.S or M.S degree in electrical engineering with 12+ years related experience.
• Hands‑on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs.
• Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (Ser Des, DDR, PCIe, CXL).
• Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent); specific tool experience is valuable but not mandatory.
• Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment) for physical design hand‑off.
• Experience with Verilog/System Verilog is required.
• Basic to intermediate knowledge of JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation.
• Hands‑on experience with DFT methodologies is a plus and considered equivalent familiarity.
• Familiarity with JTAG‑based post‑silicon debug flows and bring‑up strategies for SoC IO validation.
• Experience with boundary scan cell behavior and test access port (TAP) signal verification is a plus.
• Scripting experience or knowledge is a plus.
• Excellent analytical, communication (written and verbal), and documentation skills.

Travel: 0% – 25%.

Physical attributes:
Hearing, Seeing, Talking, Works Alone, Works Around Others.

Physical requirements:

80% sitting, 10% standing, 10% walking, 100% inside.

We offer a total compensation package that includes competitive base pay, restricted stock units, and quarterly bonus payments. Health benefits begin day one. Retirement savings plans and an industry‑leading ESPP program with a 2‑year look‑back feature are also provided.

The annual base salary range for this position, which could be performed in the US, is $91,000 – $232,000.*

* Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc. is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to Know Your Rights:
Workplace Discrimination is Illegal Poster.