Director, ASIC Design & Front-End Implementation

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Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next.

We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

Lead the ASIC Design and Front-End Implementation organization responsible for delivering next-generation networking ASICs that power HPE Networking products and technology roadmaps. Drive RTL design execution, implementation readiness, design quality, and milestone delivery from architecture through tapeout, silicon bring-up, and product deployment. Partner closely with Architecture, Verification, Emulation, Software/SDK, Physical Design, Post-Silicon Engineering, Product Management, and Product Marketing to ensure successful execution and alignment with business objectives.

• Lead RTL design and microarchitecture teams developing complex networking ASICs.
• Drive design execution from architecture through RTL completion, ensuring performance, power, area (PPA), quality, cost, and schedule targets are met.
• Establish design methodologies, coding standards, and engineering best practices.
• Review and approve key architectural and implementation trade-offs.

• Partner with Physical Design teams to achieve floor planning, timing closure, power optimization, DFT integration, and tapeout readiness.
• Ensure RTL designs are optimized for implementation, manufacturability, scalability, and production readiness.
• Support issue resolution through implementation, silicon validation, and bring-up.

• Collaborate across Architecture, Verification, Emulation, SDK/Software, Physical Design, Post-Silicon Engineering, Product Management, and Product Marketing.
• Align product requirements, architecture, RTL implementation, verification, software enablement, and deployment plans.
• Lead design reviews, milestone assessments, technical risk evaluations, and issue resolution.

• Contribute to ASIC technology strategy and product roadmaps through technical feasibility, cost, performance, and schedule analysis.
• Collaborate with Architecture and Product teams to define future networking ASIC capabilities and competitive differentiation.
• Represent the design organization in roadmap reviews, executive discussions, and customer engagements.

• Drive execution across multiple ASIC programs, managing schedules, dependencies, risks, and deliverables.
• Lead engineering managers and senior technical contributors while recruiting, developing, and retaining top talent.
• Foster a culture of accountability, technical excellence, innovation, and continuous learning.

• Improve design quality, engineering productivity, and execution efficiency through automation, CI/CD, and modern development practices.
• Champion AI-assisted engineering tools and methodology enhancements that improve predictability, quality, and time-to-market.

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of ASIC development experience, including 8+ years leading engineering teams and managers.
• Expertise in RTL design, Verilog/System Verilog, microarchitecture development, synthesis, CDC, linting, timing closure, and ASIC implementation flows.
• Proven success delivering complex ASICs from concept through production.
• Strong cross-functional (Architecture, Verification, Physical Design, Software, Emulation, and Post-Silicon) leadership, communication, and program execution skills.

• Experience with networking ASICs, switching/routing architectures, packet processing, QoS, security,…