HW SoC​/IP modeling and performance​/power analyst Senior or Staff Engineer Sophia-Antipolis or Guyancourt

Noc Architect

Qualcomm is a global leader in wireless technology and innovation. Our cutting-edge solutions power the world's most advanced mobile, automotive, networks and IoT devices. We are seeking a talented NoC Architect to join our dynamic team in Qualcomm France-QITC and contribute to the next generation of semiconductor designs.

Qualcomm Interconnect Technology Center (QITC) has been breaking ground in interconnect design for 15 years by providing more efficient SoC NoC with faster time to market than existing bus interconnects and continues to innovate and deliver technology in line with the very latest evolutions in SoC design. Our work is at the backbone of the SoC, interconnecting all major IP solutions at Qualcomm.

As a performance-analyst, the candidate will model complex HW SoCs/IPs and analyze the architecture efficiency of on-chip communication networks.

The candidate shall be able to understand and develop HW models using C/C++/SystemC and other tool/languages at different levels of abstraction, be capable of analyzing complex data patterns, identifying problem sources, challenging and of proposing solutions to identify architecture performance/power issues. We expect the candidate to contribute to prototyping methodology evolutions and improvements.

The candidate shall be able to work in a multicultural environment and have a great team spirit. Technical proficiency in English is required, French is recommended.

Preferred Qualifications

Minimum 4-6 years' work experience in microelectronics.

Skills:

Computer Networks, Bus protocols, Operating Systems, Compilers, CPU/GPU Architecture, Memory Architecture, ISA, Data Analytics, Performance Analysis, SoC/IP Modeling.

Programming languages: C/C++, Python, HDL (VHDL or Verilog).

Tools:
Git, shell, make/CMake, Pandas, Numpy.

The candidate should be able to work in a multicultural environment and have great team spirit.

Technical proficiency in English is required (French nice to have).

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.

* References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.