ASIC Physical Design Engineer, Senior

Positron AI is building next-generation AI inference accelerators designed from the ground up for low-latency, high-throughput large language model inference. Our first-generation ASIC, Asimov, is a cutting-edge accelerator targeting frontier AI workloads, with additional generations already underway.

Contribute to the physical implementation of Positron's AI accelerators from floor planning through tapeout. Support and help drive implementation methodology while partnering with RTL, synthesis, DFT, package, and backend design services to achieve world-class PPA.

• Support floor planning, macro placement, and power planning across Positron's AI accelerator designs.
• Drive clock tree synthesis, place and route, and routing optimization through to timing closure on assigned blocks.
• Contribute to signal integrity, IR/EM closure, ECO implementation, and metal fill to deliver signoff-quality results.
• Support tapeout signoff for physical implementation deliverables.
• Contribute to methodology for power grids, power/ground tiles, and bump planning.
• Assist in building congestion analysis and wire estimation approaches to support early floorplan decisions.
• Support partitioning and hierarchical implementation strategies for complex, multi-block designs, under guidance from senior/principal leads.

• Execute Innovus-based implementation flows for assigned blocks.
• Apply hands‑on expertise across Innovus, ICC2, Tempus, Prime Time, Voltus, Red Hawk, and Calibre.

• Drive closure across timing, power, area, congestion, DRC, LVS, EM, IR, and yield for owned blocks.

• Partner closely with backend design services to align on implementation strategy and execution.
• Participate in implementation quality reviews.

• Apply AI-enabled techniques for automated QoR analysis, congestion prediction, routing prediction, and floorplan optimization.

• 5–8 years of experience in physical design, spanning floor planning through tapeout.
• Experience contributing to one or more advanced-node tapeouts.
• Strong proficiency in Innovus and/or ICC2 implementation flows.
• Solid working knowledge of physical implementation, including floor planning, clock tree synthesis, timing, and power closure.
• Experience supporting signoff across timing, power, and related quality metrics.

• Experience with AI accelerator design.
• Familiarity with large SRAM arrays.
• Experience with Ser Des and LPDDR interfaces.
• Exposure to chiplet architectures and 2.5D advanced packaging.

This role is posted at the Senior level. We are a growth‑oriented organization and are open to discussing scope with candidates whose experience aligns more closely with a more senior track. This job description serves as a focused but generalized overview; specific responsibilities will be tailored to the experience of the final hire.

Success in this role looks like reliable execution on assigned blocks, strong QoR contributions, and growing ownership of implementation methodology as you develop within the team.

• Help build the physical implementation methodology for a new class of AI inference accelerators from the ground up.
• Work at the cutting edge of advanced-node design, tackling some of the hardest problems in power, timing, and signal integrity for frontier AI workloads.

The base salary range for this role is $150,000 – $250,000.

Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.

At Positron AI, we value the unique…