FPGA Software

About the Role

We're looking for an experienced FPGA/RTL engineer to help build the digital backbone of our compute payload — the hard-real-time logic that connects high-speed image sensors to embedded compute. You ll design and own RTL for sensor interfacing, high-throughput pixel capture into DDR via DMA, and memory-mapped register interfaces to embedded Linux running on ARM-based SoCs. This is active development on a live flight program with near-term launch milestones: you ll join a small, senior team, take full ownership of work streams from day one, and see your designs fly.

• Design, implement, and verify RTL in System Verilog/Verilog for the compute payload s FPGA subsystems, from architecture through on-orbit operation

• Develop high-speed camera sensor interfaces, including sensor clocking, configuration, register read/write control, and deterministic pixel capture pipelines

• Architect and implement high-throughput datapaths moving pixel data into DDR memory via DMA, with attention to bandwidth, latency, and determinism

• Build memory-mapped register interfaces (AXI) between FPGA logic and embedded Linux running on ARM cores, and define the hardware/software contract with flight software engineers

• Own timing closure, synthesis, and implementation across Zynq Ultra Scale+, Versal, and Cyclone 10 targets using Vivado and related tool chains

• Develop test benches and simulation environments to verify designs before hardware, and validate on the bench with logic analyzers, oscilloscopes, and protocol analyzers

• Support Petalinux platform bring-up, device tree configuration, and driver-level integration of FPGA peripherals with the embedded Linux stack

• Lead board bring-up and hardware integration for new payload avionics, working closely with electrical and embedded software engineers

• Investigate anomalies spanning the sensor-to-software chain, perform root cause analysis, and drive fixes across hardware/firmware/software boundaries

• Document designs and interfaces, and pair with teammates to spread ownership of the FPGA function across the team

• Contribute to build automation, regression testing, and CI for FPGA development workflows

• Bachelor s degree in Electrical Engineering, Computer Engineering, or a related field

• 5+ years of experience in FPGA/RTL design, including architecture, RTL coding, verification, synthesis, and timing closure

• Proficiency in System Verilog or Verilog for production FPGA development

• Hands-on experience with FPGA + ARM SoC platforms (e.g., Xilinx/AMD Zynq or Zynq Ultra Scale+) and AMD/Xilinx tool chains (Vivado, Vitis, Petalinux)

• Experience designing high-speed digital interfaces and DDR/DMA-based datapaths

• Experience integrating FPGA logic with embedded software, including memory-mapped register interfaces and driver-level debugging

• Hands-on hardware bring-up and lab debugging experience with oscilloscopes, logic analyzers, and embedded debug tools

• Demonstrated ability to own open-ended design problems independently and carry them from hardware

• Master s degree in Electrical Engineering, Computer Engineering, or a related discipline

• Experience in aerospace, defense, semiconductor, or other high-reliability development

• Experience with image sensor interfaces and camera pipelines (e.g., MIPI CSI-2, LVDS/SLVS, SubLVDS) or other high-bandwidth sensor front-ends

• Familiarity with Versal ACAP architecture and/or Intel/Altera devices (Cyclone 10) and Quartus toolflows

• Experience with simulation and verification tools such as Questa/Model Sim, Xcelium, or Verilator, and with UVM or other structured verification methodologies

• Working knowledge of embedded Linux internals — device trees, kernel drivers, userspace/hardware interaction — on ARM platforms

• Proficiency with C/C++, Python, and TCL for bring-up, test automation, and tooling

• Experience with hardware-in-the-loop testing and automated regression of FPGA designs

• Familiarity with fault-tolerant design and radiation effects mitigation (SEU scrubbing, TMR, configuration memory integrity) for space applications

• Experience thriving in fast-paced, high-ownership environments with rapid iteration cycles