Technical Director, NPI Packaging Technology and Assembly Engineering
Listed on 2026-02-16
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Engineering
Electrical Engineering, Electronics Engineer
Technical Director, NPI Packaging Technology and Assembly Engineering
Location:
San Diego, CA, US
pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor’s 30‑year legacy of technology advancements and strong IP portfolio but with a new mission—to enhance Murata’s world‑class capabilities with high‑performance semiconductors. With a strong foundation in RF integration, pSemi’s product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare.
From headquarters in San Diego and offices around the world, pSemi’s team explores new ways to make electronics for the connected world smaller, thinner, faster and better.
Job Summary The Technical Director, NPI Packaging Technology and Assembly Engineering will lead a small but broad team of engineers and work with RFIC design teams to develop, design, and implement pSemi world‑wide packaging, assembly, and prototype manufacturing processes. Additional responsibilities include competitive benchmarking, technology roadmap generation, feasibility studies, packaging cost analysis, risk assessment, product packaging specification for pSemi NPI projects, and PCB layout.
This person will work hand in hand with RFIC design teams and the operations group to bring cutting edge wireless products to market. This position will report directly to the Sr. Director, RFFE Product engineering.
This position has responsibility for:
- Lead and manage small teams of packaging and layout engineers
- Develop a package and assembly roadmap to meet pSemi business unit goals in collaboration with the operations packaging team
- Lead and collaborate with Design & Operations to develop differentiating packaging standards and flows
- Work closely with the IC design teams on pSemi NPI project package technology, package design, and package selection
- Work with the EM and layout teams to enable standards and drive best practices across the company
- Work collaboratively as required with Operations for vendor & technology selection, cost analysis, qualification, production ramp, and RMA investigation of bumped and packaged products manufactured at pSemi off‑shore assembly subcontractors
- Advise management on roadmap for new suppliers to meet pSemi Business Unit and Operations team goals
- Drive continuous improvement in design for cost and more aggressive design rule implementation
- Participate in technical audits of vendors and subcontractors in collaboration with Operations
Minimum Qualifications (Experience and Skills)
- Minimum of 15 years of experience in semiconductor packaging and assembly process development
- 8 years of management experience
- Strong written and verbal communication skills
- Ability to manage multiple complex, high visibility projects in parallel
- Expertise with assembly process development, characterization and qualification for advanced high volume manufacturing processes
- Experience with wafer bumping, singulation, wirebond and flip chip assembly, organic laminate and ceramic substrate technology, Wafer Level CSP (WLCSP), System in Package (SIP), embedded die technology, and lead frame packaging
- Experience with package design tools such as Autocad, Cadence Allegro / APD, Zuken
- Experience generating assembly and package drawings for vendors, customers, and data sheets
- Knowledgeable about package electrical / thermal / stress modeling and characterization
- Knowledgeable about RF and power dissipation as it relates to packaging requirements
- Experience generating customer application notes and supporting RMA investigations
Preferred Qualifications
- Strong working knowledge and experience working with Asian subcontract bump and assembly suppliers
- Familiarity with EM concepts and techniques for optimizing impedances, ground inductances, and isolation
- Familiarity with EMI concepts and modeling techniques
- Demonstrated ability to use statistical analysis tools (such as JMP) and concepts, including proficiency in formal Design…
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