Field-Programmable Gate Arrays Engineer; FPGA

MUST BE A US CITIZEN (ITAR REQUIREMENT). Support a Fortune 500 Aero-Defense Company as a FPGA/Digital Engineer.

• BS + 5 years of experience in related STEM field; MS + 3 years of experience.
• Significant hands‑on current experience in the field of VHDL design.
• Candidate must have working knowledge of formal engineering development process, VHDL design and verification.

• 8 or more years of professional technical experience.
• Experience with VHDL design and OSVVM verification for FPGA firmware.
• Experience with AMD/Xilinx series including Zynq, Kintex, Ultrascale, Versal family of devices.
• Experience with Communication Protocols (I2C, SPI, UART, PCIe, Ethernet).
• Experience with Electronic Design Automation (EDA) tools:
  Vivado, Quartus, Questa Sim.
• Knowledgeable in FPGA physical constraints and achieving timing closure.
• Generation of test benches and support of formal VHDL verification.
• Experience with board RO system level debug using test equipment such as oscilloscopes and logic analyzers.
• Experience with translating systems requirements into programmable logic requirements, design documents, and test specifications.
• Candidate should have hands on experience with DoD communications systems.