Cellular ASIC Design Engineer

Summary

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better.

It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something.

Do you excel at crafting elegant solutions to complex challenges? Do you naturally prioritize the significance of every detail? As a member of our Hardware Technologies group, you’ll contribute to designing, optimizing, and manufacturing our next-generation, high-performance, power-efficient cellular chips and system‑on‑chips (SoC). Your role will be pivotal in ensuring that Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.

By joining this group, you’ll be responsible for developing and building the technology that powers Apple’s devices. We invite you to join us in delivering the next groundbreaking Apple products!

As a Cellular ASIC Design Engineer, you’ll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power optimization, and design technology co‑optimization. You’ll design innovative products at the block/IP‑level and system‑level in advanced process technologies (3nm, 2nm and beyond).

Your primary responsibilities will involve developing best‑in‑methodologies for optimizing Power, Performance, Area, and Cost efficiency metrics through various approaches:

• Establish design guidelines, methodologies, and standards for synthesis, place‑and‑route, timing closure, and sign‑off processes
• Develop and optimize EDA tool flows including synthesis tools (DC/DCT/DCG/Genus/Oasis), P&R tools (ICC2/Fusion/Innovus/Aprisa), and sign‑off tools (PT/PT‑SI/Tempus)
• Drive timing convergence process improvements across design teams to enhance design PPA and yield
• Create and maintain comprehensive design flows, scripts, and automation tools to improve design productivity and reduce turnaround time

• Identify utilization bottlenecks in physical design and develop architectural, design, and implementation‑level solutions to improve utilizations
• Work with physical design teams on timing closure, collaborating with CAD teams, IP teams and Design Technology teams for flow scripts/tools development and validation
• Understand RTL to GDS digital flow and provide hands‑on contribution for timing signoff of complex SOCs

• Perform design technology co‑optimization analysis, including optimal operating point analysis for performance/power curves and identification of scaling trends and bottlenecks in advanced technology nodes
• Conduct Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation
• Perform timing package validation across advanced process technologies and timing signoff specification development
• Conduct in‑depth analysis of design databases and silicon validation data to identify critical issues and improve overall design metrics
• Understand intricate timing paths (digital, analog, mixed signal) and timing constraints, providing solutions as required

• Develop and implement voltage scaling and power optimization methodologies including clock gating, power gating, and dynamic voltage/frequency scaling techniques
• Use power analysis tools (Red Hawk/Sea Hawk/Voltus) for comprehensive power signoff and optimization
• Facilitate and drive STA methodology improvements using industry‑leading timing tools and ECO methodologies

• Collaborate closely with technology and IP teams to enhance efficiency through custom and semi‑custom IP development
• Work…