Senior Design Verification Engineer - QGOV

Company

Qualcomm Technologies, Inc.

Engineering Group > ASICS Engineering

• Familiarity with RTL design in Verilog and System Verilog
• Develop verification methodology, ensuring a scalable and portable environment across simulation and emulation
• Develop test plans to verify hardware building blocks, design macros, and standard interfaces (PCIE, DDR, USB, I2C, SPI, etc.)
• Own end‑to‑end DV tasks: code test benches and test cases, write assertions, run simulations, and achieve all coverage goals
• Explore innovative DV methodologies (formal, simulation, and emulation‑based) to continuously improve test bench quality and efficiency
• Develop and maintain emulation environments to collect metrics related to emulation performance

Must be located in San Diego and available for full‑time, 5‑day work week.

Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.

Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.

• 5+ years of work experience with RTL/FPGA design (Verilog) and embedded system architecture
• 5+ years of Design Verification, Emulation, and Debug experience with simulation, emulation, and prototyping flows

Relevant experience of 2‑3+ years in any of the mentioned domains (Design/Verification/Implementation) is desirable.

• Knowledge of communication protocols such as AXI4‑x, DDRx, PCIe, etc.
• Strong System Verilog/UVM‑based verification skills & experience with assertion & coverage‑based verification methodology
• Good understanding of chip‑level functional model building
• Good understanding of OOP concepts and experience with HVL such as System Verilog, UVM/OVM & System C
• Knowledge of behavioral and structural models and familiarity with simulation environments
• Experience customizing and debugging make‑based build flows and working with Xilinx’s Vivado tools
• Experience with version control tools such as Git and Gerrit
• Experience with formal/static verification methodologies (plus)
• Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs (plus)
• Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog
• Experience with C/C++ DPI transactors and monitors
• Experience with debugging tools such as JTAG and lab test equipment (logic analyzers, oscilloscopes, signal generators, etc.)
• Experience with GLS and scripting languages such as Perl, Python (plus)
• Linux OS proficiency

The ideal candidate is a self‑starter with strong initiative, discipline, motivation, and a focus on quality. The candidate must be a team player and be flexible and open to a variety of task assignments within the team.

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
• OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
• OR PhD in Science, Engineering, or related field

Qualcomm is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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The salary above reflects the broad, minimum to maximum pay scale for this position. Additionally, Qualcomm offers a competitive annual discretionary bonus program and opportunities for annual RSU grants. Benefits support your success at work, at home, and  more details, refer to Qualcomm's U.S. benefits information.

If you'd like more information about this role, please contact Qualcomm Careers.