IC Package Design Engineer

Position: IC Package Design Engineer, Staff
Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ years of System/Package Design/Technology Engineering or related work experience. OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 3+ years of System/Package Design/Technology Engineering or related work experience. OR PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ year of System/Package Design/Technology Engineering or related work experience.

Basic knowledge in high-speed IO interfaces and electromagnetic field. Knowledge of IC packaging structures and package-board interaction. Basic knowledge of electronic packaging process and typical failure modes preferred. Proven fundamentals in electrical, material, thermal, or mechanical engineering fields. Familiarity with various sophisticated package configurations and assembly/substrate technology (Flip chip BGA, 2.5D/3D Interposer, etc.). Experience in package design and proficiency in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP).

Basic understanding of some SI/PI tools (Xtract

IM, Power

SI, HFSS, Q3D, etc.), package model extraction, S-parameters, and RLGC model. Basic knowledge of substrate manufacturing process, structure, design rules, and material properties. Proven understanding of high-speed interfaces, including DDR, PCIe, UCIE, etc.

Experience with Calibre tool and package design reviews. Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs). Solid understanding of Design Rules Check and Design for Manufacturing.

Experience with 2.5D Si-Bridge design in Virtuoso or similar CAD tools is a plus. Own and drive advanced package selection, new generation product package structure, and configuration optimization. Responsible for Package/SIP physical design and layout, optimization, DV, and tape out. Work with multi-functional teams to achieve optimized mechanical, electrical SI/PI, and thermal performance for various types of chips. Work with IC PD team on top level floor planning including hard macro block placement, paring, RDL and bump pattern/assignment Drive methodology, innovations, and efficiency improvements in package design together with vendors and developers on feature development and bug resolution.

Explore, evaluate, and develop new CAD tools, design, and verification flow. Working with marketing/IC/product teams on competitive analysis and road mapping package technology for future products