Digital Design Engineer

Salary Range: $139, annually

• 3 weeks of vacation to start (120 hours/year)
• 10 paid holidays annually
• Competitive pay
• 401(k) with company match
• Medical, dental, and vision insurance
• Life insurance
• Flexible Spending Account (FSA)
• Employee Assistance Program (EAP)
• Paid time off to volunteer
• Onsite gyms, walking tracks, and employee gardens at larger locations
• Long-tenured team (many with 30+ years of service!)
• Inclusive and diverse workforce
• A company philosophy rooted in doing the right thing as a human being

Exempt: Yes

Safety Sensitive: No

The Staff Digital Design Engineer will contribute to the development of advanced phased array antenna modules and high-performance communication systems. This role combines system-level digital design involvement of Phase Array Antenna Modules with hands‑on digital ASIC/SoC development, including RTL design, verification, subsystem integration, and silicon implementation support. Have a strong background in digital design and SoC development, along with an interest in working across system, firmware, and physical design domains.

• Design and implement digital subsystems for phased array and communication system applications
• Develop high-quality RTL (System Verilog) for control and data path logic
• Participate in system architecture and partitioning
  , collaborating with RF, firmware, and system teams
• Integrate processor-based subsystems (e.g., RISC‑V) into complex SoC designs
  • SPI / QSPI
  • High‑speed serial interfaces (e.g., JESD
    204B/C or similar)
• Collaborate with firmware teams supporting embedded software development (C)
• Support verification activities and contribute to adoption of UVM and/or formal methodologies
• Work closely with physical design teams to
  • Analyze and resolve timing issues
  • Support synthesis and place‑and‑route flows
  • Develop and implement engineering change orders (ECOs)
  • Participate in system bring‑up, validation, and debug
• Perform any other related duties as required or assigned

Experience with simulation, debugging, and verification workflows;
SoC integration with processor subsystems, preferably RISC‑V; familiarity with embedded software interaction, including C programming; timing analysis and closure; synthesis and backend design collaboration; ECO generation and implementation; working knowledge of common hardware interfaces (SPI, QSPI, high‑speed serial links). 6+ years of experience in digital ASIC/SoC design. Bachelor’s or Master’s degree in Electrical Engineering or related field.

• Strong problem‑solving and debugging skills
• Ability to work effectively in cross‑functional teams
• Clear communication and documentation skills
• Interest in both system‑level and implementation‑level design challenges

Not indicated.

The above statements are intended to describe the work being performed by people assigned to this job. They are not intended to be an exhaustive list of all responsibilities, duties and skills required. The duties and responsibilities of this position are subject to change and other duties may be assigned or removed at any time. This position may require exposure to information subject to US Export Control regulations, i.e.: the International Traffic and Arms Regulations (ITAR) or Export Administration Regulations (EAR).

All applicants must be US persons within the meaning of US regulations.

Kyocera International, Inc. values diversity in its workforce, and is proud to be an AAP/EEO employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability. If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process, or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Kyocera International, Inc.

Human Resources team directly. Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.