Staff Engineer; Design Verification

Location: San Diego, CA
Duration: 12+ Month Contract

Design Verification Engineer for high-speed mixed-signal IP (PCIe, USB, MIPI, DDR, etc.), supporting full lifecycle from pre-silicon to post-silicon for 5G, AI/ML, IoT, and automotive applications.

• System Verilog/UVM verification methodology
• ASIC simulation/formal tools (VCS, Xcelium, Questa, Jasper Gold, VCFormal)
• High-speed protocols: PCIe, USB, MIPI, DDR, UFS
• SVA assertions, debugging, coverage closure
• Strong verification/testbench development experience

• Define pre/post-silicon test plans based on specs
• Develop test benches (System Verilog/UVM, mixed-signal, low power)
• Write assertions (SVA), testcases, coverage models
• Perform debugging and ensure coverage closure
• Collaborate with design, analog, SoC, and integration teams
• Support post-silicon validation

• Low power (UPF), formal & gate-level verification
• Mixed-signal IP verification (Ser Des, PLL, ADC/DAC, sensors)
• Scripting (Python/Perl)
• VIP development for Ser Des/PHY

• Bachelor’s/Master’s in EE/CE or related
• 5+ years ASIC design verification experience