Sr​/Principal GPU Engineer - Geometry​/Tiler Microarchitecture

Position: Sr. Staff/Principal GPU Engineer - Geometry/Tiler Microarchitecture
About the Team With Media Tek's leadership in SoC design, the Media Tek GPU IP team is committed to developing industry-leading, feature-rich, and highly PPA-competitive graphics IP. Our GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications. The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation.

Positions are available in our San Diego and San Jose offices.

Position Overview We are seeking a Senior Staff / Principal GPU Engineer specializing in Geometry and Tiler Microarchitecture to help define and develop next-generation GPU IP. The ideal candidate will have deep experience in graphics hardware architecture, microarchitecture specification, RTL implementation, performance analysis, and PPA optimization. In this role, you will drive the design and optimization of GPU geometry, tiling, binning, raster front-end, and cluster-level microarchitecture.

You will collaborate closely with architecture, software, compiler, performance, RTL, verification, physical design, and post-silicon teams to deliver best-in-class GPU IP for mobile, automotive, laptop, IoT, and ASIC markets. Role and Responsibilities
· Define and develop GPU cluster-level microarchitecture specifications for industry-leading graphics IP.
· Lead microarchitecture design for GPU geometry and tiler-related blocks, including primitive processing, tiling, binning, raster front-end, scheduling, and workload distribution.
· Drive PPA optimization across power, performance, and area for complex GPU subsystems.
· Collaborate with architecture and software teams to translate product requirements, API behavior, workload characteristics, and performance targets into hardware specifications.
· Work closely with RTL design, verification, physical design, software, compiler, and performance teams to identify and resolve architectural, microarchitectural, and implementation bottlenecks.
· Analyze GPU workloads and performance data to optimize geometry throughput, tiler efficiency, memory bandwidth, cache locality, load balancing, and power efficiency.
· Guide GPU IP development through the full lifecycle, including microarchitecture definition, RTL implementation, verification, synthesis, timing closure, tape-out, bring-up, and post-silicon debug.
· Debug and resolve complex pre-silicon and post-silicon issues related to functionality, performance, power, and area.
· Influence future GPU architecture directions through technical analysis, workload studies, performance modeling, and competitive benchmarking.
· Apply AI-assisted tools and automation to improve productivity in RTL development, functional debug, performance analysis, and PPA exploration.
· Deliver high-quality technical results while meeting project milestones, schedules, and product requirements.
· Build trusted and effective working relationships across internal teams, external partners, and cross-site engineering organizations.
· Contribute to best-in-class GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC applications.

Main Requirements and Qualifications

* · BS, MS, or PhD degree in Computer Science, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

* · 10+ years of experience in RTL design, microarchitecture, or architecture for complex GPU, graphics, processor, or high-performance SoC subsystems.

* · Strong hands-on experience with System Verilog, Verilog, VHDL, C/C++, and scripting languages such as Python, Perl, or Tcl.

* · Solid understanding of computer architecture, GPU architecture, SoC architecture, memory hierarchy, interconnects, and performance/power trade-offs.

* · Proven experience defining or implementing microarchitecture specifications for complex hardware blocks.

* · Experience with performance analysis, bottleneck identification, power optimization, area…