System Modeling Engineer

Company

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what’s possible to enable next‑generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

The infrastructure IP Team consists of a multi‑disciplinary group involved in the definition and design of Platform infrastructure HW components such as Interconnect (NOC), System Cache, Memory controllers and System MMU that are implemented in all Qualcomm SoCs. This position primarily involves studying System Performance using cycle‑accurate/approximate models and supporting both Infra IP level u‑architecture optimizations as well as System level application performance verification.

The ideal candidate should demonstrate the ability to understand the HW u‑architecture of the Infrastructure components involved, in particular the memory system and interconnect, identify performance bottlenecks, define experiments and conduct data‑driven performance analyses and debug using simulation; and partner effectively with IP designers, Design Verification teams and System performance architects.

This is a challenging position, working on most innovative technologies, surrounded by experts but also by users of our technology all over the world.

You will contribute to evaluating performance of future envisioned hardware architectures and providing key data points to decision makers. You will participate to develop a key architecture modeling platform and support its continuous improvement.

• Participate in architecture exploration campaigns working closely with key architects from various teams. Analyze complex dataset to identify insights and patterns that will help define the requirements for next‑generation SoCs.
• Support on exploratory methodology projects, involving machine learning, data science, etc.
• Expand, maintain and document innovative modeling frameworks. Participate in defining a new hardware modeling semantic, breaking up with conventional hardware programming languages.

• Robust understanding of computer architecture and memory hierarchy.
• Strong knowledge of Object Oriented Programming (C++, Python).
• Interest for programming paradigms.
• Knowledge in bus components micro‑architecture.
• Understanding of performance/power/area trade‑off.
• Ability to quickly react and adapt to changes.
• Excellent communication skills.

• Degree in Microelectronics, Computer Science, or related field.
• Preferably 2‑5 years of solid experience in SoC modeling and/or software development; new graduates will be considered upon strong internships & motivation.
• Understanding of interconnect protocols like AHB/AXI/ACE/ACE‑Lite/NoC concepts.
• Experience in Data Science, Machine Learning.

• Master’s or PhD degree in Microelectronics, Computer Science, or related field.
• Strong mathematical background.
• Knowledge in network traffic engineering.
• Knowledge of Memory Controller, LPDDR & DDR protocols.
• Experience with performance verification and driving micro‑architecture investigations on blocks like memory controller, CPU, GPU, NoC and multi‑media is a plus.

• Bachelor’s degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master’s degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑ or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.

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