Engineer, |Engineer

Job Description:

This position requires 2-5 years of experience with STA closure and Place and Route. Exposure to ICC, Innovus, and/or Prime Time is needed. Hands on experience with the latest Fin Fet technologies (20nm and below) is needed.

Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our CPU core design team. As a high‑speed physical design engineer you will develop, implement, and verify high‑speed processor cores using state‑of‑the‑art tools and technologies.

You will be part of a team responsible for the complete Physical Design Flow for high‑speed processor cores. Tasks involve the development and enablement of low‑power implementation methods, customized P&R to achieve area reduction and performance goals, and the development of high‑speed customized logic cells.

Additional responsibilities in this role involve a good understanding of functional, test (DFT) mode constraints for place and route, floor planning, power planning, IR drop analysis, placement, multi‑mode & multi‑corner (MMMC) clock tree synthesis, routing, timing optimization, 2.5D RC extraction, signal integrity, cross‑talk noise and delay analysis, debugging timing violations for multi‑mode and multi‑corner designs, implementing timing fixes, rolling in functional ECOs, physical verification (drc, lvs, antenna), debugging and fixing violations and formal verification.

The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and

C. This individual will design, verify and deliver complex modem CPU Physical Design solutions from netlist and timing constraints to the final product.

• Candidates must have 8-12 years of direct relevant experience in Physical Design, floor planning, P&R, formal verification, and/or physical verification.
• This position requires 2-5 years of experience with STA closure and Place and Route. Exposure to ICC, Innovus, and/or Prime Time is needed. Hands on experience with the latest Fin Fet technologies (20nm and below) is needed.

• Required - Bachelor's degree in Science, Engineering, or related field.

• 8+ years of direct industry experience in Physical Design.
• Place & Route tool experience on Cadence Innovus and/or Synopsys ICC
  2.
• Timing closure experience in Synopsys PTSI.
• Formal verification experience.
• Physical verification experience.
• Master's degree in Electrical Engineering.

Must be local to San Diego, Bay Area or Austin, TX. Will be required to come on‑site once staff returns to campus.