Memory System Architect, Silicon

Note:

By applying to this position you will have an opportunity to share your preferred working location from the following:
Mountain View, CA, USA;
San Diego, CA, USA
.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in micro-architecture and design of ASIC blocks.
• Experience in designing/implementing Register-Transfer Level (RTL) for one or more blocks:
  Central Processing Units (CPUs), Graphics Processing Units (GPUs), caches, Memory Management Units (MMUs), or coherent fabrics.
• Experience in micro‑architecture/design performance analysis, tools, and simulators.

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
• Experience in building build time configurable designs.
• Knowledge in one or more of these areas: coherent interconnects, caches, memory systems.
• Knowledge of Hardware Description Languages (HDL) such as System Verilog or Verilog.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct‑to‑consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will shape the future of our coherent memory systems for consumer SoCs. You will leverage your technical expertise in design and uArch to create the most advanced power‑and performance‑efficient mobile coherent systems. Your work will have a direct impact on the performance, efficiency, and innovation of our next‑generation devices. You will work with hardware designers and validation teams to build and test exceptional hardware architectures.

As part of this work, you will participate in the development of technology in the memory system and the filing of associated patents.

• Explore and evaluate different uArch and design choices for power‑and performance‑efficient coherent and non‑coherent memory systems.
• Author hardware uArch specification for next‑generation coherent and non‑coherent memory systems.
• Analyze performance and power trade‑offs.
• Work with hardware design, verification, emulation, and validation teams to build and test the hardware architecture.

US: $163,000 - $237,000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law.

See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc.

stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.