NoC Interconnect Design Engineer and Architect

##
Company:

Qualcomm Technologies, Inc.

## Job Area:

Engineering Group, Engineering Group >ASICS Engineering

General

Summary:

The NoC bus team group consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery to the SoCs. One aspect of the process is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best power interconnect.

Candidates should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.

Responsibilities:

The successful applicant will be responsible for creating micro-architecture bus components specifications as well as analyzing the performance results, deliver RTL and run tool flows. Responsibilities also include evaluating new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC. Candidate should also be able to deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the interconnects.

Skills/

Experience:

* Knowledge of various bus protocols (AHB, AXI, CHI, …), network on chip.

* Strong working knowledge of architecture tradeoff analysis

* Strong knowledge of ASIC flow (synthesis, STA, Lint), power tools

* Skills for trouble shooting and problem solving, including RTL design, FPGA and post-silicon debug

* Ability to define bus components micro-architecture with knowledge of performance/power/area tradeoff.

* Ability to quickly react and adapt to changes.

* Excellent communication skills.

* Familiarity with CPU architecture is a big plus.

Minimum Qualifications:

* Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

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EEO

Employer:

Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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Pay range and Other Compensation & Benefits:

$ - $

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).

In addition, our highly competitive benefits package is designed to support your success at work, at home, and r recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.