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Implementation Timing​/STA Design Engineer

Job in San Diego, San Diego County, California, 92189, USA
Listing for: Qualcomm
Full Time position
Listed on 2026-06-21
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Test Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 210000 USD Yearly USD 140000.00 210000.00 YEAR
Job Description & How to Apply Below
Position: Implementation Timing / STA Design Engineer

Overview

Qualcomm Technologies, Inc. is a leading technology innovator pushing the boundaries of what's possible to enable next-generation experiences and drive communication and data processing transformation to help create a smarter, connected future for all.

The Qualcomm's SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, static timing analysis (STA), and timing closure for premium-tier chips. This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM.

Scripting skills in Tcl, Perl, or Python are also desirable.

Principal Duties and Responsibilities
  • Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis.
  • Collaborate closely with RTL design and physical design teams to identify timing requirements and bottlenecks.
  • Generate, review, and validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores.
  • Review and integrate HM constraints into SoC and ensure correlation between HM and SoC timing.
  • Analyze timing across modes and corners, understand concepts like path pessimism and margins.
Minimum Qualifications
  • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Pay and Benefits

Pay range: $ - $.

In addition to a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus), Qualcomm offers a highly competitive benefits package designed to support your success at work, at home, and at play.

EEO Statement

Qualcomm is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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