Senior PMIC Design Engineer

Job Description

We are seeking a Senior Staff Engineer, Analogue PMIC Design to serve as a technical leader and key contributor within the analog ASIC organization. This role is responsible for end to end ownership of complex power management architectures, including specification, circuit design, simulation, verification, and delivery of production ready PMIC IP. The Senior Staff Engineer partners closely with system architects, digital design, verification, and layout teams to guide technical decisions, solve the most complex analog challenges, and ensure robust performance across all operating conditions.

This position plays a critical role in shaping power architecture strategy, mentoring engineers, and driving design quality and execution across multiple programs.

• Definition of the architecture for the complex Power-management blocks, plan and execute the development of the blocks and providing the necessary documentation to different departments for the characterization of the block.
• Responsible for the delivering the fully verified blocks and may get involved in the verification of power-management subsystems within the Analogue section of a chip.
• Solves complex problems in a tightly constrained environment.
• Fully competent in Analogue design for complex sub-cells and small subsystems.
• Keeps abreast of new developments and is technical expert in the design of analogue sub-cells.
• Ensures quality of the solution; works with macro lead to ensure timely delivery of subsystems.

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity/affirmative action employer that believes everyone matters. qualified candidates will receive consideration for employment regardless of their race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances.

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• Bachelor's degree, master's degree, or PHD in Science, Engineering, or related field
• 10+ years of experience in analog or mixed signal IC design
• Experience of using Cadence and Mentor analogue design and verification tools
• hands on ownership of PMIC or power related IP blocks
• Experience delivering fully verified blocks to tape out
• Experience on low power consumer or mobile SoCs - Experience supporting bring up or validation teams
• Design experience of Key Power management IPs like SMPS, LDOs
• Experience with additional power blocks such as bandgaps, references, charge pumps, or clock generators
• Exposure to automotive or high reliability power designs
• Familiarity with low power system level architecture tradeoffs
• Familiarity with CMOS process technologies