Sr. Design Verification Engineer - Digital

Location

San Diego, CA (Hybrid)

Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading edge products.

The Sensing Product Group located in our San Diego office has unique expertise in system level platform solutions for Sensing Products including Touch & Proximity. These are leading edge low power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance. These ultra-small, feature-rich sensing systems are optimized for a wide range of battery-powered, portable applications such as smartphones, laptops, tablets, wearables, handheld devices and other consumer or ITA control applications.

The Sr. Integrated Circuit (IC) Verification Engineer is responsible for developing and implementing verification plans for a variety of mixed-signal integrated circuit blocks and systems. The Sr. Integrated Circuit (IC) Verification Engineer will closely collaborate with system, digital & physical design, embedded firmware, analog, and cross functional teams.

The role also includes technical leadership, mentoring and supervision of junior verification engineers, pre-silicon validation, and support to silicon validation, production test and application engineers.

• Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%)
• Design and implement complex test benches using System Verilog and UVM methodology. Perform block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Debug complex simulation failures and identify root causes in design or verification environments. Improve verification scalability and portability from project to project by environment enhancement and tools automation.
  
  Generate and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (30%)
• Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%)
• Supervise and mentor junior verification engineers. (15%)
• Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%)
• Support silicon lab evaluation, performance characterization and debug. (5%)
• Technical support to test, product and application engineers. (5%)

• 8+ years of industry experience in integrated circuit design verification (DV)
• B.S. or M.S. in Electrical or Computer Engineering
• Strong analytical, synthesis and problem solving skills
• In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM
  32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals.
• Proficiency in System Verilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens)
• Demonstration of technical leadership
• Experience with standard hardware protocols (I2C, I3C, SPI, MIPI)
• Independent, self-motivated, rigorous, innovating, team player and able to follow through
• Excellent verbal and written communication skills

• Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application
• Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL
• Experience with consumer and/or ITA market circuit developments

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.

We are proud to be an EEO employer M/F/D/V. We maintain a drug-free workplace.

The estimated pay range for this position is $130,000 - $183,206. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee’s total compensation package.