Data Center Power & Limits Architect

Job Title

Data Center Power & Limits Architect

1. Power & Limits Architecture Definition

• Define holistic power, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels
• Architect power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O
• Develop strategies to maximize performance under datacenter-level constraints (rack power caps, cooling limits, PUE targets)

2. Dynamic Control & Optimization

• Architect advanced dynamic power control systems (e.g., DVFS/DCVS, AVS-like systems) for fast transient response
• Design closed-loop control systems using telemetry and feedback to optimize performance vs. constraints
• Develop proactive and reactive limit management (thermal throttling, power capping, workload shaping)

3. Telemetry & System Integration

• Define requirements and interfaces for telemetry infrastructure (sensors, BMC, firmware, system SW)
• Enable real-time monitoring and decision making across system layers
• Ensure integration with platform controllers (e.g., BMC/EC, rack management, orchestration layers)

4. Cross-Layer Co-Design

• Collaborate with:
  • Silicon/SoC architects (power islands, regulators, sensors)
  • Platform teams (VRs, PDN, cooling)
  • Software/firmware teams (power management algorithms)
  • Data center infrastructure teams (rack-level optimization)
• Define hardware/software partitioning for limits enforcement with minimal overhead

5. Modeling, Simulation & Validation

• Develop system-level models (MATLAB/Simulink, architectural simulators) to:
  • Predict performance vs. power/thermal constraints
  • Evaluate algorithms and architecture trade-offs
• Perform workload-driven analysis to validate architecture decisions

6. Innovation & Future Architecture

• Drive innovations in:
  • Power delivery efficiency
  • Thermal-aware scheduling
  • AI workload-aware limits
  • Rack/cluster-level power orchestration
• Define next-generation architectures to support scaling AI/HPC performance under constrained infrastructure

• 10+ years of experience in power architecture, system architecture, or related domains
• Deep expertise in:
  • Power management systems and limits control
  • Thermal and electrical constraints in high-performance systems
  • DVFS/DCVS, power capping, and control systems
• Strong understanding of:
  • Data center/server architecture (CPU/GPU/accelerators, memory systems)
  • Power delivery networks (VRs, PDN, rack power distribution)
  • Telemetry, sensors, and system monitoring
• Experience with modeling and analysis tools (e.g., MATLAB, Python)

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).

In addition, our highly competitive benefits package is designed to support your success at work, at home, and r recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.