Physical Design Engineer

Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software.

The Graphics team is looking for Experienced Physical Design Engineers to work on Adreno Graphics cores in the area of Physical Implementation.

The Physical Implementation Engineer will work in Qualcomms Adreno GPU team and will be responsible for all the P&R experiments targeted at validating new flows/methodologies.

Able to deal with MSM Top level complexity from FP, Placement, CTS, Routing and timing closure. Must be able to take the Hardmacro through P&R from Netlist to GDS including timing closure, formal and Physical verification.

• Floor planning: at Full chip level or Macro or Block Level
• Macro placement, power grid implementation, power routing, special routing analog signals etc
• Power collapse/Low power implementation flow
• P&R: Place and route at chip level or block level, perform placement, timing closure in P&R mode, perform clock tree synthesis, routing etc
• Timing closure/STA:
• Perform STA using Primetime Si or Tempus or any industry standard STA engine, timing closure, ECO generation, timing correlation
• Deep understanding of timing skills to perform correlation, timing fixes , corner/voltage definitions etc
• Clock Tree Synthesis:
• Perform custom or regular clock tree implementation at block level or top level
• Clock tree balance of complicated tree, clock power reduction techniques etc
• Low Power Implementation:
• Power collapse/power gain techniques/implementation
• UPF/CPF flow knowledge
• CLP/FV
• Physical Verification Using Calibre:
• Running all the PV checks (DRc/LVS/ERC/Softcheck ) and deep understanding of all the rules and fixes
• Perl/Python/Shell script experience is also preferred to help with automation

All your information will be kept confidential according to EEO guidelines.