Digital Design Engineer

Company:

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

Qualcomm’s high-speed parallel interfaces team is looking for a motivated and driven ASIC front-end design engineer to work with a world-class global team tasked to architect, design, and implement industry-leading DDR and die‑to‑die interfaces fueling the company’s growth in high-speed compute and server domains.

The Digital Design Engineer will be responsible for designing, developing RTL, and implementing digital IPs that serve the systems connecting SoC to DRAM devices and provide reliable high-speed links in multi-die systems. In this existing role you will work closely with systems architecture, verification, timing, and physical design engineers to design and implement control and data‑path blocks for SoC interfaces. The ideal candidate will have experience on high speed, low power digital logic design development with hands‑on experience on ASIC front‑end implementation tool flow methodologies and silicon bring‑up.

• Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, and gate‑level simulation debug.
• Position requires working closely with cross‑functional teams to enable all phases of implementation and silicon bring‑up.
• Prior experience with high‑speed parallel physical interfaces designs and low power designs is a plus.

• Bachelor’s Degree in Science, Engineering, or related field.
• Minimum 4 years ASIC design, verification, or related work experience.

• BS with 4 years or MS with 2 years relevant work experience.
• Ideal candidate will have experience on high speed, low power digital logic design with hands‑on experience on ASIC front‑end implementation tool flows and silicon bring‑up.
• Expertise required on digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices and analysis, low power implementation and sign off, design for test (DFT) flows for stuck and TDF modes, gate‑level simulation bring‑up and debug.
• Position requires working closely with cross‑functional teams in a high‑paced and dynamic environment to enable all phases of implementation and silicon bring‑up.
• Prior experience with high‑speed parallel physical interfaces designs and low power designs is a plus.

Qualcomm is an equal opportunity employer. Qualcomm is committed to providing an accessible process for individuals with a disability, and has an established accommodation procedure. Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other protected class.

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We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.