Physical Design Engineer

Physical Design Engineer – Wireless RF Silicon

Location:

San Diego, CA

Type:
Contract

Role Overview

• The client is developing next-generation silicon to power a global Low Earth Orbit (LEO) satellite communications network. The Wireless RF Silicon team is seeking a Physical Design Engineer to drive backend implementation and physical closure of complex, high-performance SoCs used in advanced wireless and RF systems.
• In this role, you will partner closely with RTL, architecture, and sign-off teams to translate designs into manufacturable silicon while balancing aggressive power, performance, and area (PPA) targets.

Key Responsibilities

• Partner with RTL and logic design teams to evaluate architectural feasibility and drive early physical design studies.
• Explore and optimize power–performance–area (PPA) tradeoffs to ensure successful physical design closure.
• Own block-level and chip-level physical implementation, including:
• Logic synthesis
• Floor planning and partitioning
• Bus and pin planning
• Place and route
• Power and clock distribution
• Perform and resolve congestion analysis, timing closure, and physical optimization.
• Execute IR drop and power integrity analysis and drive mitigation strategies.
• Lead physical verification, ECO implementation, and final sign-off.
• Collaborate cross-functionally to resolve design issues and support tape-out milestones.
• Maintain high standards for quality, documentation, and design robustness in a fast-paced development environment.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong experience with ASIC physical design and backend implementation flows.
• Hands-on proficiency with industry-standard EDA tools, including:
• Fusion Compiler
• StarRCXT
• Red Hawk-SC
• Calibre
• Prime Time SI (PTSI)
• Solid understanding of timing analysis, power integrity, clocking strategies, and physical verification methodologies
• Experience working closely with RTL and logic designers in a full-chip or complex block environment

Preferred Qualifications

• Experience supporting wireless, RF, or mixed-signal So Cs
• Exposure to advanced process nodes and high-performance designs
• Familiarity with low-power design techniques and multi-voltage domains
• Experience in silicon bring-up, tape-out support, or post-silicon debug is a plus
• Strong communication skills and ability to work effectively in cross-functional teams