Engineer|Engineer

Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, Client, Sensors, etc.) for exciting products targeted for 5G, AI/Client, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system‑level concept to tape out and post‑silicon support.

• Define pre‑silicon and post‑silicon test plans based on design specs and using applicable standards while working closely with the design team.
• Architect and develop the testbench using advanced verification methodology such as System Verilog/UVM, analog/mixed‑signal simulation, low‑power verification, formal verification, and gate‑level simulation to ensure high design quality.
• Implement power‑aware verification methodology in SV/UVM environment to support coverage and assertions.
• Author assertions in SVA, develop test cases and coverage models, debug, and ensure coverage closure.
• Work with digital design, analog circuit design, modeling, controller/subsystem, and SoC integration teams to complete successful PHY‑level verification, integration into subsystem and SoC, and post‑silicon validation.

• Master's or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 2 years of ASIC design verification or related work experience.
• Knowledge of a HVL methodology such as System Verilog/UVM.
• Experience with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jasper gold, or similar.

• Experience with low‑power design verification, formal verification, and gate‑level simulation.
• Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.
• Experience in scripting languages (Python or Perl).
• Experience with mixed‑signal IP design verification, including USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, data converters (DAC, Client), or sensors.