Gen, -Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer
Job in
San Diego, San Diego County, California, 92189, USA
Listed on 2026-07-08
Listing for:
Nutanix
Full Time
position Listed on 2026-07-08
Job specializations:
-
Engineering
Hardware Engineer, Systems Engineer, Electronics Engineer, Test Engineer
Job Description & How to Apply Below
Company:
Qualcomm Technologies, Inc.
Job Area:
Engineering Group, Engineering Group ASICS Engineering General
Summary:
Job Description Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory No
Cs based Subsystem Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory subsystems.. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1
Ghz+) designs in QCT products.
The candidate will work on architecture, design (RTL coding), and deployment of the next generation, high-speed memory subsystems into QCT products. You will develop or contribute to the development of architecture and design specifications and drive the micro-architecture of portions of the logic design. You will implement and deliver RTL and work with verification engineers to deliver high quality designs. You will be responsible for debugging your designs and also provide debug support when integrated into the rest of the chip.
Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power Analysis are expected to be key tasks. You will make regular contributions to the overall improvement in design methodology to drive productivity and quality of results.
Qualifications Bachelor's or Masters degree in Science, Engineering, or related field.
5 + years ASIC design, RTL coding, front-end digital design experience3+ years Hardware Architecture experience
Preferred Qualifications 3-10 years of ASIC design (RTL coding) Preferred Exposure to RTL Design Verification flows is a plus3+ years of direct Hardware Architecture experience
Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design Master's degree preferred
Experience with the following:
LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors
Exposure to HBM memory type designs
On-chip tightly coupled SRAM & L3 cache controller architecture/design
Experience with x86 or ARM CPU/bus architectures
Ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification
Education Requirements
Required:
Bachelor's, Computer Engineering and/or Electrical Engineering Preferred:
Master's, Computer Engineering and/or Electrical Engineering
Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
ORMaster's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
ORPhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disabili or call Qualcomm's toll-free number found here . Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
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EEO
Employer:
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range and Other Compensation & Benefits :$ - $The above pay scale reflects the broad,…
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