Physical Design Engineer​/Senior Engineer level

Physical Design Engineer

Qualcomm Technologies' Digital ASIC team is seeking talented Physical Design Engineers to join our SoC and Core Design organization. In this role, you will be responsible for implementing complex digital designs using industry-leading methodologies and EDA tools, contributing to the delivery of high-performance and power-efficient products.

You will participate in the complete physical design flow for sophisticated SoCs and IPs, including GPU, Camera, Multimedia, DDR, Modem, Audio, and other cutting-edge semiconductor solutions. This position provides the opportunity to work on advanced implementation techniques, low-power methodologies, and optimization strategies that improve performance, power efficiency, and silicon area.

Key Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floor planning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement engineering change orders (ECOs) and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
• Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 2+ years of industry experience or relevant academic/project experience in Physical Design.

Preferred Qualifications

• Experience in one or more of the following areas:
• ASIC/SoC Physical Design implementation.
• Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
• Static Timing Analysis and timing closure using Synopsys Prime Time SI.
• Physical verification and design sign-off methodologies.
• Formal verification techniques and tools.
• Power domain implementation and low-power design methodologies.
• Clock Tree Synthesis (CTS), routing, and timing optimization.
• Signal integrity, noise analysis, and MMMC sign-off flows.
• DFT-aware physical implementation and constraint management.
• Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.

Pay range and Other Compensation & Benefits: $ - $