Static Timing Analysis (STA) ​/ Timing Closure & Signoff Engineer - San Diego, Santa Clara, CA

Position Title:Static Timing Analysis (STA) / Timing Closure & Signoff Engineer
Location: San Diego, CA (preferred) or Santa Clara, CA or Austin, TX (5 days on-site)
Contract Duration: 12+ months

About the Role:
We are hiring Static Timing Analysis engineers to strengthen the timing signoff team supporting a leading SoC manufacturer on advanced-node designs. In this role you will own timing constraints, drive block- and full-chip timing closure across all modes and corners, and collaborate closely with the physical design, synthesis, and DFT teams to deliver clean, silicon-ready timing signoff.
The ideal candidate has strong fundamentals in static timing analysis, hands-on experience with industry signoff tools, and a proven track record of closing timing on complex, high-frequency designs at advanced FinFET technology nodes.

• Timing constraints (SDC):
  Develop, review, validate, and maintain timing constraints — clock definitions, generated clocks, I/O delays, false paths, multicycle paths, and clock-domain-crossing (CDC) exceptions — and ensure constraint consistency and quality.
• Timing signoff:
  Perform block-level and full-chip static timing analysis and signoff using Synopsys Prime Time / Prime Time SI (and/or Cadence Tempus) across a full multi-mode multi-corner (MMMC) setup.
• Timing closure:
  Analyze and close setup, hold, recovery/removal, and transition/capacitance violations; generate and implement timing ECOs and coordinate fixes with the place-and-route team.
• Signal integrity:
  Run crosstalk delay and noise (SI) analysis, identify and resolve SI‑induced violations, and correlate with extraction and physical data.
• Parasitic correlation:
  Set up and validate RC parasitic extraction and SPEF (StarRC / Quantus QRC), manage RC corners, and ensure extraction‑vs‑signoff correlation.
• Variation‑aware analysis:
  Apply OCV / AOCV / POCV (SOCV) derating methodologies and drive accurate margin‑aware signoff.
• Hierarchical timing:
  Build and validate timing abstracts / interface models (ETM / ILM), perform interface timing budgeting, and support top‑level integration for hierarchical designs.
• Low‑power timing:
  Handle UPF‑based multi‑voltage / multi‑power‑domain designs, including level shifters, isolation cells, and power‑aware timing checks.
• Flow & automation:
  Automate and enhance timing analysis and ECO flows using TCL / Python / Perl; improve turnaround time and reporting.
• Collaboration & signoff quality:
  Work with synthesis, P&R, CTS, DFT, and IR/EM teams; document methodology, present timing reviews, and provide silicon‑ready signoff sign‑off criteria and reports.

• Strong fundamentals in static timing analysis — setup/hold, recovery/removal, timing arcs, slack, path groups, clock latency, uncertainty, and derating concepts.
• Hands‑on experience with Synopsys Prime Time / Prime Time SI for block and/or full‑chip timing signoff.
• Proficiency in SDC constraint development, debug, and validation (clocks, I/O timing, exceptions, CDC).
• Experience with MMMC (multi‑mode multi‑corner) analysis and closure.
• Understanding of OCV / AOCV / POCV variation‑aware timing methodologies.
• Working knowledge of crosstalk / signal‑integrity analysis and noise closure.
• Familiarity with parasitic extraction and SPEF (StarRC / Quantus QRC) and RC corner concepts.
• Solid understanding of the physical design flow — synthesis, place‑and‑route, and clock tree synthesis — and its interaction with timing.
• Exposure to advanced technology nodes (16nm / 7nm / 5nm / 3nm FinFET).
• Strong scripting skills in TCL (mandatory);
  Python or Perl for flow automation.
• Good debugging skills, clear communication, and the ability to work in a cross‑functional, delivery‑driven team.

• Experience with Cadence Tempus / Quantus signoff tools.
• Low‑power design exposure — UPF, power domains, level shifters, and isolation cells.
• Hierarchical timing signoff, timing budgeting, and ETM / ILM model generation and validation.
• IR‑drop / electromigration awareness and exposure to Ansys Red Hawk / Cadence Voltus (rail‑aware timing).
• DFT timing knowledge — scan, ATPG, and test‑mode (shift/capture) timing closure.
• Formal SDC / constraint verification tools and glitch / dynamic‑power awareness.
• Experience across multiple full tapeouts from RTL‑to‑GDSII signoff perspective.

Candidates across the 3–8 year band are welcome. Depth of ownership and independence are expected to scale with experience:

• Block-level SDC development and timing closure; setup/hold and SI debug.
• Timing ECO generation and support under guidance; extraction and MMMC runs.
• Contributes to flow scripts and signoff reports.