Physical Design (Multiple levels United States of America ASICS Enginee

## Physical Design (Multiple levels)
San Diego, California, United States of America
* Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
* Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
* Perform floor planning, partitioning, power planning, and IR-drop analysis.
* Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
* Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
* Perform RC extraction, physical verification, and formal verification activities.
* Implement engineering change orders (ECOs) and support design convergence through sign-off.
* Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
* Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
* Develop automation and productivity tools using scripting languages and software development techniques.
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
* ** 2-10+
** years of industry experience or relevant academic/project experience in Physical Design.
* Experience in one or more of the following areas:
* ASIC/SoC Physical Design implementation.
* Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
* Static Timing Analysis and timing closure using Synopsys Prime Time SI.
* Physical verification and design sign-off methodologies.
* Formal verification techniques and tools.
* Power domain implementation and low-power design methodologies.
* Clock Tree Synthesis (CTS), routing, and timing optimization.
* Low power implementation techniques experience
* Signal integrity, noise analysis, and MMMC sign-off flows.
* DFT-aware physical implementation and constraint management.
* Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
* Perl/Tcl, Python skills are needed.
* Strong problem solving and ASIC development/debugging skills.
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** Pay range*
* ** and Other Compensation & Benefits****:
** The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation  also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).

In addition, our highly competitive benefits package is designed to support your success at work, at home, and r recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this .If you would like more information about this role, please contact.