Director, Yield Architecture & Engineering United States of America ASICS Engineering Posted a day ago

Company:

Qualcomm Technologies, Inc.

Engineering Group, Engineering Group > ASICS Engineering

We are seeking an engineering leader with strong software, automation, governance, and team-building experience to serve as Director, Automation within the Yield Management team in Process Packaging Solutions. This role will lead the next phase of automation for yield engineering by building the systems, workflows, dashboards, and AI-enabled tools that make the team’s work more predictable, visible, and repeatable.

A central part of this role is to institutionalize how the team operates. The leader will automate governance processes and create operating rhythms that make project plans, reviews, decisions, lessons learned, CAPA, dashboards, and status reporting easier to run and sustain. The leader will ensure every major initiative has a clear why, what, who, and when; every review closes with owners and dates;

and lessons learned feed back into repeatable workflows. The role will also build a more connected team culture by creating shared standards, common tools, and operating rhythms that help distributed engineers work from shared expectations and a common operating model.

• Governance Automation and Operating Discipline:
  Build and automate the team’s core governance processes, including project planning, intake, prioritization, roadmap tracking, operating reviews, lessons learned, CAPA tracking, decision logs, dashboards, KPIs, and status reporting. Ensure each major initiative clearly defines why the work matters, what will be delivered, who owns it, and when it will be completed. Capture lessons learned and CAPA outcomes as institutional memory, not one-off knowledge.
• Automation Strategy and
  
  Roadmap:
  
  Define and execute the automation roadmap for yield management, diagnostics, analytics, engineering operations, and reporting. Prioritize work based on business impact, engineering time saved, quality improvement, risk reduction, and readiness for new technology programs such as advanced packaging, 3
  
  DIC, and large compute products.
• Software, Data, and AI Systems:
  Lead the development of robust automation frameworks, data pipelines, dashboards, engineering applications, and AI-enabled decision-support systems. Evolve workflows from traditional scripts to scalable platforms, then to AI-augmented systems that improve signal detection, root-cause analysis, reporting, and corrective-action speed.
• Team Building and Culture:
  Build a connected, collaborative automation function across sites and disciplines. Create shared standards, operating rhythms, and team practices that reduce silos, strengthen collaboration, and help engineers work together from a common operating model.
• Cross-Functional Workflow Integration:
  Partner with yield, diagnostics, design, DFT, product and test engineering, failure analysis, process technology, IT, EDA vendors, and manufacturing stakeholders to connect data, tools, and decisions across the silicon lifecycle. Translate expert workflows into repeatable systems without taking ownership away from domain experts.
• Technical Team Leadership:
  Lead, coach, and develop a distributed automation team. Build talent depth in software engineering, data engineering, AI, infrastructure, and semiconductor workflow automation. Reduce single points of failure through documentation, code quality, reusable platforms, cross-training, and succession planning.
• Continuous Improvement and Capacity Creation:
  Drive a continuous-improvement mindset that uses automation to reduce manual effort, improve quality, and free senior engineering capacity for higher-value priorities. Treat efficiency gains as capacity to redeploy toward strategic work, not simply as cost reduction.

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 6+ years of ASIC design,…