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Phased Array Frontend Engineer, Architecture & Simulation

Job in San Diego, San Diego County, California, 92101, USA
Listing for: Apex Systems
Full Time position
Listed on 2026-08-24
Job specializations:
  • Engineering
    Systems Engineer
Job Description & How to Apply Below

Phased Array Front-End Architecture & Simulation Engineer (D2D + Broadband, Tx/Rx)

Location:

San Diego, CA

Role Summary

Architect and simulate phased array front-end performance for both D2D and broadband Ka-band satellite payloads. Define front-end architecture (Tx and Rx chains), build predictive models to verify architectural choices, and confirm system requirements are met through simulation-based verification.

Responsibilities

  • Define front-end architecture:
    Tx/Rx chain topology, component partitioning, gain/power/NF distribution, PA/LNA placement and specification
  • Verify architecture meets system-level requirements through simulation: EIRP, G/T, OOBE, sensitivity, dynamic range
  • Build and maintain PA and LNA behavioral models to predict array-level performance
  • Validate DPD/APT architectural decisions through closed-loop simulation
  • Perform architecture trade studies: efficiency vs. linearity, noise vs. gain distribution, single-vs-multi-stage, back-off allocation
  • Support hardware verification by correlating measured component data to architectural models

Hardware Knowledge Required

Front-End Architecture

  • Tx/Rx chain architecture definition: gain staging, power budget, NF allocation, linearity allocation
  • PA specification derivation:
    Psat, P1dB, PAE, OIP3 targets from system EIRP/ACLR requirements
  • LNA specification derivation: NF, gain, IP3, stability margin targets from system G/T and interference requirements
  • Architecture partitioning: front-end vs. beam former boundary, IF vs. RF beamforming implications on front-end
  • Multi-temperature architecture margin: performance budgets at 25°C/50°C/85°C corner cases

Transmit Chain Modeling

  • Nonlinear PA behavioral models (Volterra, memory polynomial, Rapp, Saleh), AM-AM/AM-PM, thermal derating
  • DPD architecture verification: LUT, GMP, convergence performance, coefficient stability
  • ET/APT: supply modulator modeling, efficiency vs. linearity tradeoffs
  • OOBE: spectral regrowth, ACLR/ACPR, spectral mask compliance (3

    GPP NTN, ITU)
  • Tx array performance: beam-dependent EIRP, active element patterns, scan loss, cross-factor

Receive Chain Modeling

  • LNA noise modeling: NF vs. frequency/temperature/bias, noise parameters (NFmin, Γopt, Rn)
  • NF cascade: multi-stage noise figure, gain distribution, system noise temperature
  • Receiver sensitivity: MDS, SNR budget from antenna to ADC
  • Interference tolerance: blocker desensitization, IMD3/IMD5, receiver intermodulation
  • Rx array performance: G/T, beam-dependent sensitivity, noise correlation

Array-Level Architecture Verification

  • Active element patterns, mutual coupling, scan loss, grating lobe analysis
  • Beamforming: beam weight application, quantization effects, multi-beam interference
  • Cross-pol and cross-factor: inter-element coupling, polarization purity vs. scan
  • Architectural verification: confirming component specs roll up to meet system performance

Regulatory & Compliance

  • 3

    GPP  emission masks, ITU RR Article 22 EPFD limits
  • Co-existence analysis, sensitivity/selectivity requirements

Software Skills Required

  • MATLAB/Simulink: PA/LNA behavioral modeling, DPD algorithm simulation, Tx/Rx link budget tools, array performance Monte Carlo, architecture trade study frameworks
  • Python:
    Signal processing, batch simulation automation, data pipeline, trade study scripting
  • Keysight ADS:
    Harmonic balance, X-parameter models, load-pull simulation, noise analysis, circuit-level architecture validation
  • 3

    GPP waveform tools
    : OFDM/SC-FDMA, ACLR/EVM, spectral mask verification

NOT Required for This Role

  • Antenna element EM design (HFSS, CST)
  • PCB layout tools (Allegro, Altium)
  • FPGA/RTL design
  • Mechanical CAD
  • Manufacturing/NPI/yield
  • Package physical design

Qualifications

Required

  • MS or PhD in EE (RF, Communications, or Signal Processing)
  • 5+ years RF front-end architecture and simulation experience
  • Expert MATLAB/Simulink user for behavioral modeling and system simulation
  • Experience defining PA/LNA specifications from system requirements
  • Tx and Rx chain analysis (OOBE/ACLR + NF/sensitivity)
  • Phased array front-end architectural tradeoff experience
  • Familiarity with 3

    GPP  satellite communication standards

Preferred

  • Multi-band architecture experience (cellular frequencies + Ka-band)
  • DPD/APT architecture definition and simulation
  • NTN or satellite direct-to-device system experience
  • Experience correlating architectural predictions with measured hardware data

Deliverables

  • Front-end architecture specification (Tx and Rx) for D2D and broadband Ka
  • PA/LNA behavioral model library for architectural verification
  • Architecture trade study reports with performance predictions
  • Simulation-based verification that architecture meets system requirements
  • DPD/APT architecture recommendation with supporting analysis
  • Component specification documents derived from system requirements
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